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FPSLIC / AVR  seminar's


Atmel is hosting a series of seminars for the FPSLIC and AVR till the end of February.
I attended the seminar in Sacramento and i urge you to do the same, as you not only get vital information for developing
with the AVR and FPSLIC but also a free STK300 , a 30$ discount voucher for the purchase of an STK 500 (so you can get an STK 500 for 49$) and a nice FPSLIC t-shirt :-)

stk500-voucher.jpg (15159 bytes)

On top of that you get to meet the Atmel guys (and girls) up-close and personal and they will answer all your development questions.
atmel-seminar.jpg (17443 bytes)
(From left to right Wendy Lockhart, Joel Rosenberg, Bard Pedersen and Detlef Schick)

Check this link for more details on dates and locations.

Here is a brief overview of what we have been told. First the AVR stuff

For those of you who are not familiar with the AVR family you will get an overview of the architecture, development tools,
code examples and comparisons for code size between AVR and other mcu's.

For me the most interesting part was one of the upcoming reference designs which include an AVR embeded web server starter kit.
avr-webserver.jpg (13468 bytes)
It will provide a low level Ethernet interface, tcp/ip stack, HTTP, FTP ,e-mail support and a file system for storing web pages and data. The web "board" is at production and expected to be availiable end of 1st Q 2001.

The other intresting part to existing AVR users is the next generation of AVR controllers.
There are going to be "shrunk" versions of the existing parts, with reduced power consumption and improved instruction set.
Clock speed is going to double (@5V) and with the added instructions for integer and and fractional multiplication of both signed and unsigned numbers the AVR will be able to replace some DSP designs.

The new devices will include some new peripherals like

Two wire interface
On chip voltage reference
Brown out detector
and Reset flags

The new silicon will also have improvents on existing peripherals including an update external memory interface, which will allow the easier intergration of memory maped peripherals.
On the analog part and I/O the new parts will have

Improved Power-On reset
Enhanced Brown-Out detector
Enhanced A/D converter
and internal voltage references

For the I/O all pins will be able to sink and source 20mA and the noise emissions will be reduced

FPSLIC is a combination of an AVR and an FPGA core in the same silicon, with advanced development tools that allow you to design and verify both the software and  FPGA in an intergraded enviroment.

The AVR part has all standard peripherals like timers, UART's, 2wire interface, watchdog and I/O and has a 30K static RAM that can be partioned between program and data areas.   Since the program is stored into RAM the AVR can execute at approx. 20 MIPS @ 25 MHz.
The FPGA can range from 5K gates to 40K and can also access the internal RAM through an allready intergraded memory interface, so that you don't have to waste any of the gates for the memory interface.

What i found extremely interesting (except the speed) is that the FPSLIC can be re-configured partial or in total dynamicaly.
This means that you can use the AVR to "re-program" either all or part of the FPGA and also change its code "on the fly".

As we have been told, there is also an ARM based FPSLIC under development.

Very interesting are also the development tools that support FPSLIC. They are FPSLIC "customized" versions of standard HDL development and verification tools.

Check the FPSLIC page at Atmel's web site for more info.

This page was last updated 12/02/2001