From odiessel@cse.unsw.EDU.AU Wed Dec  3 17:30:11 2003
Date: Mon, 10 Nov 2003 19:25:35 +1100 (EST)
From: Oliver Diessel <odiessel@cse.unsw.EDU.AU>
To: comp3211_tutor-list@cse.unsw.EDU.AU
Subject: A3 Guide

Assignment 3 Marking Guide
--------------------------

The following guide outlines the requirements and the suggested
marking scheme for Assignment 3. The guide is organised according to
the stated deliverables for the assignment.

1. Define the sw instruction opcode and instruction format
   Insert an sw instruction using correct registers at the correct
   location into the program - this should be storing register 0 contents
   at location indicated by register 3 as the 9th instruction in the program

   5 marks overall

2. Draw the block diagram including registers for the instruction,
   the register file contents (regA and regB), the ALU output, and the
   memory data read - add control signals for the instruction register and
   PC enable

   Could have 1 or 2 memories and 1 or 3 ALUs depending upon whether or
   not the original resources were used, or they were rationalised for
   a single cycle implementation.

   10 marks in total

3. (a) Describe the register transfers for each of the 5 instruction types

       10 marks

   (b) Construct the microprogram
       - control signals for each register transfer (5 marks)
       - correct sequencing (5 marks)
       - correct dispatch tables (5 marks)

       15 marks total

   (c) Block diagram for micro-sequencer

       5 marks

   (d) VHDL model of micro-sequencer - essentially a 2 process finite-state
       machine - 1 process for next-state & output; the other process for
       micro-sequencer state update

       10 marks each process - max 15 marks if not a micro-programmed design
       (i.e. just a finite state machine implementation)

       20 marks overall

4. Modify the provided VHDL code

   i.e. processor - replace control
                  - patch in registers
                  - reroute control & data signals

        may have to add register designs & muxes
        need to modify the data memory for writing or completely
        restructure memory if both data & instruction memories are
        to be combined

   10 marks overall

5. Simulation waveforms that include:

   - clk
   - reset
   - PC address
   - instruction register contents
   - regA & B contents
   - immediate value
   - alu output
   - memory data read
   - reg write data
   - control signals (register enables, mux selects, etc.)
   - status signals (zero, negative)

   - need to check that correct number of cycles simulated and correct
     signals asserted for each instruction type
   - check correct result produced
   - check correct number of cycles overall executed - depends upon
     hardware assumptions i.e. number of cycles for each instruction type
     (there may be some variation for different datapath organisations)

   15 marks overall - 5 marks for the correct range of signals
                    - 5 marks for correct execution of each instruction type
                    - 5 marks for correct results

   Bonus up to 5 marks for good attempts to explain how to interpret
   the simulations and demonstrate their correctness

6. Calculate the original program run time (1750 ns)
   calculate the enhanced program run time (could vary a little
   depending upon number of cycles assumed for branch instructions -
   around 952 ns seems correct for minimal enhancement i.e. 3 cycles
   for both branch types)

   Determine speedup

   Explain why there has been a speedup

   15 marks altogether (5 marks each)

There may be scope for other bonuses, for example, for good argumentation
(for and against) as to why a particular choice of datapath organisation
was made - perhaps 5 marks is appropriate - please show me examples before
awarding.

Partricularly clear presentations/reports are also worth a bonus - but they
must be particularly clear - maybe 5 marks is appropriate
--

Please let me know if there is anything I have left out or if
you think a particular requirement should be marked differently.

Cheers,
Oliver