COMP3211/COMP9211 Computer Architecture

Week 3 Tutorial Exercises

Q01.  [Y3.3] Sketch the output waveform produced by the following VHDL 
      concurrent signal assignment statements:

      s1 <= '0' after 5 ns, '1' after 15 ns, '0' after 35 ns, '1' after 50 ns;
      s2 <= '0' after 20 ns, '1' after 25 ns, '0' after 50 ns;

Q02.  [Y3.6] Write and simulate the entity-architecture description of a 3-bit
      decoder using the conditional signal assignment statement. Test the model 
      with all possible combinations of inputs and plot the decoder output 
      waveform. Try to use the ISE/WebPACK tool for this and following exercises.

Q03.  Write and simulate the entity-architecture description of a single
      bit slice of a universal shifter using the conditional signal
      assignment statement. The slice should have left, right, and load
      inputs, a 2-bit direction input, and a single output bit. Test
      the model with all possible combinations of inputs and plot the
      shift slice output waveform.

Q04.  [Y3.9] Why are the concepts of delta events and delta delays
      necessary for the correct event simulation of digital circuits?

Q05.  [Y4.2] Explain why you cannot have both a sensitivity list and wait
      statements within a process

Q06.  [Y4.6] Show an example of VHDL code that transforms an input
      periodic clock signal to an output signal at half the frequency.
      Harder: Implement a procedure that doubles the input frequency.

Q07.  Model a synchronous 4-bit counter using behavioural VHDL.