COMP3211/COMP9211 Computer Architecture

Week 4 Tutorial Exercises

Q01.  [Y4.4] Consider the construction of a register file with 8
      registers, where each register is 32 bits. Implement the model
      with two processes. One process reads the register file, while
      another writes to the register file. You can implement the registers
      as signals declared within the architecture and therefore visible
      to each process.

Q02.  [Y4.9] Implement and test a VHDL model for the state machine for
      a traffic controller described in the following state table:

      Current           Next
      State     Input   State    Output
      ----      ----    ----     ----

       0         0       1        10
       0         1       2        00
       1         0       0        01
       1         1       2        00
       2         0       0        01
       2         1       2        00

Q03.  [Y5.3] You are part of a software group developing algorithms
      for processing speech signals for a new digital signal processing
      chip. To test your software your options are to construct i) a
      detailed hierarchical model of the chip comprised of gate level
      models at the lowest level of the hierarchy or ii) a behavioural
      level model of the chip that can implement the algorithms that you
      wish to use. Your goal is to produce correct code for a number of
      algorithms prior to detailed testing on a hardware prototype. How
      would you evaluate these choices and what are the trade-offs in
      picking one approach over the other?

Q04.  [Y5.5] Consider the circuit shown below. Construct a structural
      model comprised of two components: a generic N-input AND gate and
      a two-input OR gate. By passing the appropriate generic value we
      can instantiate the same basic AND gate component as a two-input
      or three-input AND gate.

      
            +---\
      ----->|    \
      ----->|AND  >----+
      ----->|    /     |    +---\
            +---/      +---->\   \
                              >OR >-->
            +---\      +---->/   /
      ----->|AND \_____|    +---/
      ----->|    /
            +---/

Q05.  [YE5.2] The goal of this exercise is to introduce trade-offs in 
      building models at different levels of abstraction and trading 
      accuracy for simulation speed.

      Step 1.

      Start with the model of a single-bit ALU provided for you under
      the VHDL models link of the course web page. This model is
      constructed with concurrent signal assignment statements.
      Replace this model with one that replaces all the concurrent
      signal assignment statements in the architecture body with
      sequential assignment statements and a single process. The
      process should be sensitive to events on input signals a, b, c_in,
      and opcode. The process should use variables to compute the value
      of the ALU output. The last statement in the process should be a
      signal assignment statement assigning the ALU output value to the
      signal result. Use a delay of 10 ns through the ALU for both result
      and c_out.

      Step 2.

      Analyze, simulate, and test this model, and ensure that all three
      operations (AND, OR, and ADD) operate correctly.
      
      Step 3.
      
      Construct a VHDL structural model of a 4-bit ALU. Use the single-bit 
      ALU as a building block. Use a ripple-carry implementation to propagate
      the carry between single-bit ALUs. Simulate and explain the output 
      waveforms you obtain.
      
      Step 4.
      
      Construct an 8-bit ALU using the 4-bit ALU as a building block.
      Use a ripple-carry implementationto propagate the carry between
      single-bit ALUs. 
      
      Step 5.
      
      Based on your construction, what is the propagation delay through 
      the 8-bit adder?  Generate a test case for each ALU instruction.  
      Run the simulation for a period equal to at least the delay through 
      the 8-bit adder.
      
      Step 6.
      
      Rewrite the 8-bit model as a behavioural model without hierarchy.
      Use a single process and the following hints:
      
        a) Inputs, outputs, and internal variables are all 8-bit vectors
           of type std_logic_vector.
        
        b) Make use of variables to compute intermediate results.
      
        c) Use the case statement to decode the opcode.
        
        d) Do not forget to set the value of the output carry signal.
      
        e) The propagation delay should be set to the delay through 
           the hierarchical structural model.
      
      Step 7.

      Test the new model.
      
      Step 8.
      
      Qualitatively compare the two models with respect to the difference
      in the number of events that occur in the flattened hierarchical 
      model and the single-level model in response to a new set of inputs.