COMP3211/COMP9211 Computer Architecture

Week 5 Tutorial Exercises

Q01.  [Y5.2] Consider a VHDL type that can take on the values (0, 1, X, U). 
      The values X and U correspond to the values unknown and uninitialized 
      respectively. Define a resolved type that takes on these values and write
      and test a resolution function for this resolved type.

Q02.  [Y5.3] Using a concurrent procedure looks very much like using a 
      component in a hierarchically structured design. What is the difference 
      between using a concurrent procedure and constructing a structural design?

Q03.  Describe using a state diagram an asynchronous handshake protocol
      as initiated by the bus master. Describe a suitable VHDL architecure
      for this side of the protocol.

Q04.  [SR3.5] What is the benefit of using a multiple-bus architecture compared
      to a single bus architecture.

Q05.  [S3.8] The VAX SB1 bus uses a distributed, synchronous arbitration scheme.
      Each SB1 device (i.e., processor, memory, I/O module) has a unique priority
      and is assigned a unique transfer request (TR) line. The SB1 has 16 such
      lines (TR0, TR1, ..., TR15), with TR0 having the highest priority. When
      a device wants to use the bus, it places a reservation for a future time 
      slot by asserting its TR line during the current time slot. At the end of
      the current time slot, each device with a pending reservation examines the
      TR lines; the highest priority device with a reservation uses the next slot.
      A maximum of 17 devices can be attached to the bus. The device with 
      priority 16 has no TR line. Why not?

Q06   [S3.9] Paradoxically, the lowest priority device usually has the lowest
      average wait time. For this reason the processor is usually given the 
      lowest priority on the SB1. Why does the priority 16 device usually have 
      the lowest average wait time? Under what circumstances would this not
      be true?