COMP3211/COMP9211 Computer Architecture

Week 6 Tutorial Exercises

Q01.  [S3.10] Draw and explain a timing diagram for a PCI write operation
      similar to Stalling, Figure 3.23 (Figure 1 in your assignment).

Q02.  Describe in VHDL and simulate a device that writes to or reads from 
      a tri-stated bus line. The interface of the device should be as follows:


                       +-------------+
               WriteIn |             |
              -------->|             | 
                       |  Bus        | TristateLine
               ReadOut |  Tranceiver |<------------>
              <--------|             |
                       |             |
                       +-------------+
                              ^ 
                             /|\ 
                              | 
                              | R/~W

Q03.  [P&H Example p.665] Suppose we have a system with the following 
      characteristics:

      1. A memory and bus system supporting block access of 4 to 16 32-bit
         words.

      2. A 64-bit synchronous bus clocked at 200 MHz, with each 64-bit
         transfer taking 1 clock cycle, and 1 clock cycle required to 
         send an address to memory.

      3. Two clock cycles needed between each bus operation. (Assume the
         bus is idle before an access.)

      4. A memory access time for the first four words of 200 ns; each 
         additional set of four words can be read in 20 ns. Assume that 
         a bus transfer of the most recently read data and a read of the
         next four words can be overlapped.

      Find the sustained bandwidth and the latency (time to complete the
      operation) for a read of 256 words for transfers that use 4-word 
      blocks and for transfers that use 16-word blocks. Also compute the 
      effective number of bus transactions per second for each case. 
      Recall that a single bus transaction consists of an address 
      transmission followed by data.

      [Hint: The answer appears in P&H, pp.665 - 666]

Q04.  [P8.12] The example above demonstrates that using larger block sizes
      results in an increase in the maximum sustained bandwidth that can
      be achieved. Under what conditions might a designer tend to favour
      smaller block sizes? Specifically, why would a designer choose a block
      size of 4 instead of 16 (assuming all characteristics are as identified
      in the example)?

Q05.  [P7.1] Describe the general characteristics of a program that exhibits
      very little temporal and spatial locality with regard to data accesses. 
      Provide an example program (pseudocode is fine). 

Q06.  [P7.2] Describe the general characteristics of a program that exhibits
      very high amounts of temporal locality but very little spatial locality 
      with regard to data accesses. Provide an example program (pseudocode 
      is fine) 

Q07.  [P7.3] Describe the general characteristics of a program that exhibits
      very little temporal locality but very high amounts of spatial locality 
      with regard to data accesses. Provide an example program (pseudocode 
      is fine).