COMP3211/COMP9211 Computer Architecture

Week 12 Tutorial Exercises


Q01. Assume that the operation times for the major functional units used in a
     processor design are the following:
        memory read: 2 ns
        memory write: 3 ns
        ALU: 2 ns
        Adder: 2 ns
        Decoder: 1ns
        register file (read or write): 2 ns
        Others: 0 ns

        1. Determine the clock cycle time if it is designed as a single cycle 
           processor.
        2. Determine the clock cycle time if it is designed as a 5 stage multicycle 
           processor. Draw a high level block diagram of the multicycle datapath
        3. For an application with instruction mix: 20% load, 10% store, 
           5% jump and 65% R-type, what is the CPI for each design? 

Q02. Based on the information given in Q01. If we redesign the muticycle datapath
     without any registers between the register file and ALU, what is the clock 
     cycle time? What is CPI?         

Q03. Figure 5.30 (on page 378 in P&H book - Slide 16 from Lecture 21 is similar) 
     shows a block level multicycle datapath design.  We can delete registers 
     A and B without affecting the functionality of the datapath. Can we delete 
     the Instruction register? Why?      

Q04. Based on the microprogram shown in Figure 5.46 (page 408, P&H's book
     & Slides 48 & 49 from Lecture 21), list the microinstructions to
     perform swap(a, b).