COMP3211/COMP9211 Computer Architecture

Week 13 Tutorial Exercises


Q01. [P&H 6.3] How could we modify the following code to make use 
     of a delayed branch slot?

	LOOP:	lw	$2,	100($3)
		addi 	$3,	$3,	4
		beq	$3,	$4,	Loop

     (there is an answer!)

Q02. [P&H 6.5] For each pipeline register in Figure 6.25 on page 467,
     label each portion of the pipeline register with the name of the 
     value that is loaded into the register. Determine the length of 
     each field in bits. For example, the IF/ID pipeline register
     contains two fields, one of which is an instruction field that is
     32 bits wide.

Q03. [P&H 6.11] Consider executing the following code on the pipelined 
     datapath of Figure 6.46 on page 492 (P&H's textbook):

		add 	$1,	$2,	$3
		add 	$4,	$5,	$6
		add 	$7,	$8,	$9
		add 	$10,	$11,	$12
		add	$13,	$14,	$15

     At the end of the fifth cycle of execution, which registers are 
     being read and which register will be written?

Q04. [P&H 6.12] With regard to the program of Q03, explain what the
     forwarding unit is doing during the fifth cycle of execution.
     If any comparisons are being made, mention them.

Q05. [P&H 6.13] With regard to the program of Q03, explain what the 
     hazard detection unit is doing during the fifth cycle of execution.
     If any comparisons are being made, mention them.

Q06. Elaborate the VHDL entity and architecture descriptions for 
     the sequencer-based control unit of a multicycle processor, as depicted 
     in block diagram form in Slides 38 & 50 of the lecture from Week 11.