COMP3211/COMP9211 Computer Architecture

Week 14 Tutorial Exercises


Q01. For Assignment 3, discuss which signals should be stimulated by
     any testbench that is designed to properly simulate the operation
     of the multicycle version of the datapath? Which signals should you
     produce waveforms for to provide a minimal yet complete and 
     comprehensive demonstration of the revised design?

Q02. What factors limit the performance of a pipelined datapath as the
     depth of pipelining is increased?

Q03. The last slide of Lecture 25 (Week 13) contains a program excerpt.
     Assume this program is to run on the 5 stage pipeline you are familiar
     with but without enhancements for data or control hazards. 

     How many cycles are needed to execute this code including the necessary
     stalls assuming the branch is taken once? (You should assume the branch 
     direction is determined in the excute stage and the PC is updated in 
     the memory access stage.)

     Describe the hazards in the code, and describe how you would eliminate
     or minimize them. Reassess the time needed to execute the code
     after the enhancements you describe have been incorporated.