library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Integration is
Port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
write_data : in std_logic_vector(31 downto 0);
Read_notWrite : in std_logic;
enable : in std_logic;
read_data : out std_logic_vector(31 downto 0);
DOUT: out std_logic_vector(31 downto 0)
);
end Integration;
architecture Behavioral of Integration is
begin
mem_process: process(enable,CLK,RESET)
variable data_mem: std_logic_vector(31 downto 0) := (
X"00000007");
begin
if RESET='1' then --asynchronous RESET active High
DOUT <= X"00000000";
elsif (enable = '1') then
if Read_notWrite = '0' then
data_mem := write_data;
else
read_data <= data_mem;
if (CLK'event and CLK='1') then
DOUT <= data_mem;
end if;
end if;
end if;
end process;
end Behavioral;
