library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dFlipFlop is
Port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
ENABLE: in STD_LOGIC;
DIN: in STD_LOGIC;
DOUT: out STD_LOGIC
);
end dFlipFlop;
architecture Behavioral of dFlipFlop is
begin
process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
DOUT <= '0';
elsif (CLK'event and CLK='1') then --CLK rising edge
if (ENABLE='1') then
DOUT <= DIN;
end if;
end if;
end process;
end Behavioral;
