library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dFlipFlop32BitRegister is
Port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
ENABLE: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(31 downto 0);
DOUT: out STD_LOGIC_VECTOR(31 downto 0)
);
end dFlipFlop32BitRegister;
architecture Behavioral of dFlipFlop32BitRegister is
begin
process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
DOUT <= X"00000000";
elsif (CLK'event and CLK='1') then --CLK rising edge
if (ENABLE='1') then
DOUT <= DIN;
end if;
end if;
end process;
end Behavioral;
