info x 182 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic
col x 324 0 0 0 0 0 0 0 
radix x 10 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 dFlipFlop32BitRegister
term mark 319 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

var add 1 0 0 226 8 10 0 0 CLKinSTD_LOGIC
var add 2 0 0 34 9 12 0 0 RESETinSTD_LOGIC
var add 3 0 0 34 10 13 0 0 ENABLEinSTD_LOGIC
var add 4 31 0 36 11 10 0 0 DINinSTD_LOGIC_VECTOR
var add 5 31 0 36 12 11 0 0 DOUToutSTD_LOGIC_VECTOR
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cell fill 3 20 0 0 0 0 0 0 1
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cell fill 3 28 0 0 0 0 0 0 1
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cell fill 4 4 0 0 0 0 0 0 00000000000000000000000000000001
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cell fill 4 16 0 0 0 0 0 0 00000000000000000000000000000100
cell fill 4 20 0 0 0 0 0 0 00000000000000000000000000000101
cell fill 4 24 0 0 0 0 0 0 00000000000000000000000000000110
cell fill 4 28 0 0 0 0 0 0 00000000000000000000000000000111
cell fill 4 32 0 0 0 0 0 0 00000000000000000000000000001000
cell fill 4 36 0 0 0 0 0 0 00000000000000000000000000001001
cell fill 4 40 0 0 0 0 0 0 00000000000000000000000000001010
cell fill 4 44 0 0 0 0 0 0 00000000000000000000000000001011
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cell fill 4 52 0 0 0 0 0 0 00000000000000000000000000001101
cell fill 4 56 0 0 0 0 0 0 00000000000000000000000000001110
cell fill 4 60 0 0 0 0 0 0 00000000000000000000000000001111
cell fill 4 64 0 0 0 0 0 0 00000000000000000000000000010000
cell fill 4 68 0 0 0 0 0 0 00000000000000000000000000010001
cell fill 4 72 0 0 0 0 0 0 00000000000000000000000000010010
cell fill 4 76 0 0 0 0 0 0 00000000000000000000000000010011
cell fill 4 80 0 0 0 0 0 0 00000000000000000000000000010100
cell fill 4 84 0 0 0 0 0 0 00000000000000000000000000010101
cell fill 4 88 0 0 0 0 0 0 00000000000000000000000000010110
cell fill 4 92 0 0 0 0 0 0 00000000000000000000000000010111
cell fill 4 96 0 0 0 0 0 0 00000000000000000000000000011000
cell fill 4 100 0 0 0 0 0 0 00000000000000000000000000011001
cell fill 4 104 0 0 0 0 0 0 00000000000000000000000000011010
cell fill 4 108 0 0 0 0 0 0 00000000000000000000000000011011
cell fill 4 112 0 0 0 0 0 0 00000000000000000000000000011100
cell fill 4 116 0 0 0 0 0 0 00000000000000000000000000011101
cell fill 4 120 0 0 0 0 0 0 00000000000000000000000000011110
cell fill 4 124 0 0 0 0 0 0 00000000000000000000000000011111
cell fill 4 128 0 0 0 0 0 0 00000000000000000000000000100000
cell fill 4 132 0 0 0 0 0 0 00000000000000000000000000100001
cell fill 4 136 0 0 0 0 0 0 00000000000000000000000000100010
cell fill 4 140 0 0 0 0 0 0 00000000000000000000000000100011
cell fill 4 144 0 0 0 0 0 0 00000000000000000000000000100100
cell fill 4 148 0 0 0 0 0 0 00000000000000000000000000100101
cell fill 4 152 0 0 0 0 0 0 00000000000000000000000000100110
cell fill 4 156 0 0 0 0 0 0 00000000000000000000000000100111
cell fill 4 160 0 0 0 0 0 0 00000000000000000000000000101000
cell fill 4 164 0 0 0 0 0 0 00000000000000000000000000101001
cell fill 4 168 0 0 0 0 0 0 00000000000000000000000000101010
cell fill 4 172 0 0 0 0 0 0 00000000000000000000000000101011
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cell fill 4 180 0 0 0 0 0 0 00000000000000000000000000101101
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cell fill 4 196 0 0 0 0 0 0 00000000000000000000000000110001
cell fill 4 200 0 0 0 0 0 0 00000000000000000000000000110010
cell fill 4 204 0 0 0 0 0 0 00000000000000000000000000110011
cell fill 4 208 0 0 0 0 0 0 00000000000000000000000000110100
cell fill 4 212 0 0 0 0 0 0 00000000000000000000000000110101
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cell fill 4 228 0 0 0 0 0 0 00000000000000000000000000111001
cell fill 4 232 0 0 0 0 0 0 00000000000000000000000000111010
cell fill 4 236 0 0 0 0 0 0 00000000000000000000000000111011
cell fill 4 240 0 0 0 0 0 0 00000000000000000000000000111100
cell fill 4 244 0 0 0 0 0 0 00000000000000000000000000111101
cell fill 4 248 0 0 0 0 0 0 00000000000000000000000000111110
cell fill 4 252 0 0 0 0 0 0 00000000000000000000000000111111
cell fill 4 256 0 0 0 0 0 0 00000000000000000000000001000000
cell fill 4 260 0 0 0 0 0 0 00000000000000000000000001000001
cell fill 4 264 0 0 0 0 0 0 00000000000000000000000001000010
cell fill 4 268 0 0 0 0 0 0 00000000000000000000000001000011
cell fill 4 272 0 0 0 0 0 0 00000000000000000000000001000100
cell fill 4 276 0 0 0 0 0 0 00000000000000000000000001000101
cell fill 4 280 0 0 0 0 0 0 00000000000000000000000001000110
cell fill 4 284 0 0 0 0 0 0 00000000000000000000000001000111
cell fill 4 288 0 0 0 0 0 0 00000000000000000000000001001000
cell fill 4 292 0 0 0 0 0 0 00000000000000000000000001001001
cell fill 4 296 0 0 0 0 0 0 00000000000000000000000001001010
cell fill 4 300 0 0 0 0 0 0 00000000000000000000000001001011
cell fill 4 304 0 0 0 0 0 0 00000000000000000000000001001100
cell fill 4 308 0 0 0 0 0 0 00000000000000000000000001001101
cell fill 4 312 0 0 0 0 0 0 00000000000000000000000001001110
cell fill 4 316 0 0 0 0 0 0 00000000000000000000000001001111
time info 50 50 10 10 50 50 1 1 psCLK
font save -14 0 400 49 0 0 0 0 Times New Roman
src mod 0 2540568064 29654341 6 0 0 0 0 dFlipFlop32BitRegister.vhd
utd false 0 0 0 0 0 0 0 0 
cellenab on 0 0 0 0 0 0 0 0 
grid on 0 0 0 0 0 0 0 0 
com add 1 0 10 225 7 0 -67 0 Waveform created by
HDL Bencher 4.1i
Source = dFlipFlop32BitRegister.vhd
Sun Aug 01 18:05:31 2004
type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO
type info 31 0 2 0 0 0 0 0 bitBITDOWNTO
type info 31 0 0 0 0 0 0 0 logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO
type info 3 0 0 0 0 0 0 0 sizeVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 UnsignedVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 machine_cycle_statesBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 7 0 0 0 0 0 0 0 memvVECTORDOWNTO
type info 7 0 0 0 0 0 0 0 STD_ULOGICBITDOWNTO
type info 7 0 0 0 0 0 0 0 1BITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_ULOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 bit_vectorVECTORDOWNTO
type info -2147483647 2147483647 0 0 0 0 0 0 integerINTEGERTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 qqBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGICBITDOWNTO
type info 2 0 0 0 0 0 0 0 mybyteVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_LOGIC_VECTORVECTORDOWNTO
val info 0 0 0 0 0 0 0 0 c_signed0
val info 0 0 0 0 0 0 0 0 c_clear0
val info 0 0 0 0 0 0 0 0 12
val info 1 0 0 0 0 0 0 0 `BR00
val info 1 0 0 0 0 0 0 0 `s44
val info 1 0 0 0 0 0 0 0 `RES5
val info 1 0 0 0 0 0 0 0 `FCWIDTH2
val info 1 0 0 0 0 0 0 0 `TCKO0
val info 1 0 0 0 0 0 0 0 `IF23
val info 0 0 0 0 0 0 0 0 c_no_override0
val info 0 0 0 0 0 0 0 0 numaddr3
val info 1 0 0 0 0 0 0 0 `IF12
val info 1 0 0 0 0 0 0 0 `OD4
val info 1 0 0 0 0 0 0 0 `N5
val info 1 0 0 0 0 0 0 0 `FDEPTH4
val info 0 0 0 0 0 0 0 0 c_add0
val info 1 0 0 0 0 0 0 0 `F_DEASSERT4
val info 1 0 0 0 0 0 0 0 `s11
val info 0 0 0 0 0 0 0 0 c_reg0
val info 1 0 0 0 0 0 0 0 `Q25
val info 0 0 0 0 0 0 0 0 width4
val info 1 0 0 0 0 0 0 0 `C_READ5
val info 1 0 0 0 0 0 0 0 `C_WRITE4
val info 1 0 0 0 0 0 0 0 `C_P_CHRG2
val info 1 0 0 0 0 0 0 0 `C_ACTIVE3
val info 1 0 0 0 0 0 0 0 `C_L_MODE0
val info 1 0 0 0 0 0 0 0 `F_IDLE1
val info 1 0 0 0 0 0 0 0 `F_ASSERT2
val info 0 0 0 0 0 0 0 0 c_unsigned0
val info 1 0 0 0 0 0 0 0 `C_NOP7
val info 1 0 0 0 0 0 0 0 `C_REFRSH1
val info 1 0 0 0 0 0 0 0 `s22
val info 1 0 0 0 0 0 0 0 `state_delay6
val info 1 0 0 0 0 0 0 0 `s33
val info 1 0 0 0 0 0 0 0 `FWIDTH32
val info 1 0 0 0 0 0 0 0 `s00
val info 1 0 0 0 0 0 0 0 `IF01
val info 0 0 0 0 0 0 0 0 440
val info 1 0 0 0 0 0 0 0 `D10
val info 0 0 0 0 0 0 0 0 c_override0
opt vhdl87 0 0 0 0 0 0 0 0 
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