info x 136 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic
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radix x 10 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 dFlipFlop
term mark 63 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

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utd false 0 0 0 0 0 0 0 0 
cellenab on 0 0 0 0 0 0 0 0 
grid on 0 0 0 0 0 0 0 0 
com add 1 0 10 163 7 0 -67 0 Waveform created by
HDL Bencher 4.1i
Source = dFlipFlop.vhd
Sun Aug 01 18:01:00 2004
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type info 3 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO
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type info 31 0 0 0 0 0 0 0 qqBITDOWNTO
type info 31 0 0 0 0 0 0 0 machine_cycle_statesBITDOWNTO
type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_ULOGIC_VECTORVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 bitBITDOWNTO
type info 31 0 0 0 0 0 0 0 bit_vectorVECTORDOWNTO
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val info 1 0 0 0 0 0 0 0 `F_IDLE1
val info 1 0 0 0 0 0 0 0 `F_ASSERT2
val info 0 0 0 0 0 0 0 0 c_unsigned0
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val info 0 0 0 0 0 0 0 0 c_signed0
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val info 1 0 0 0 0 0 0 0 `TCKO0
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opt vhdl87 0 0 0 0 0 0 0 0 
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