library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory is
Port ( address : in std_logic_vector(2 downto 0);
write_data : in std_logic_vector(31 downto 0);
Read_notWrite : in std_logic;
enable : in std_logic;
read_data : out std_logic_vector(31 downto 0)
);
end memory;
architecture Behavioral of memory is
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
begin
mem_process: process(enable)
variable data_mem: mem_array := (
X"00000000",
X"00000001",
X"00000002",
X"00000003",
X"00000004",
X"00000005",
X"00000006",
X"00000007");
variable addr: integer;
begin
addr:=conv_integer(address(2 downto 0));
if (enable = '1') then
if Read_notWrite = '0' then
data_mem(addr) := write_data;
else
read_data <= data_mem(addr);
end if;
end if;
end process;
end Behavioral;
