JDF E // Created by ISE ver 1.0 PROJECT wk02 DESIGN wk02 Normal DEVKIT xcv50-6bg256 DEVFAM virtex FLOW XST VHDL STIMULUS dFlipFlop_tbw.tbw Normal STIMULUS dFlipFlop32BitRegister_tbw.tbw Normal STIMULUS memory_tbw.tbw Normal STIMULUS Integration_tbw.tbw Normal MODULE dFlipFlop32BitRegister.vhd MODSTYLE dflipflop32bitregister Normal MODULE memory.vhd MODSTYLE memory Normal MODULE dFlipFlop.vhd MODSTYLE dflipflop Normal MODULE Integration.vhd MODSTYLE integration Normal [STRATEGY-LIST] Normal=True, 1091366950
Make your own free website on Tripod.com