library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu1bit is
Port ( a : in std_logic;
b : in std_logic;
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic;
c_out : out std_logic);
end alu1bit;
architecture Behavioral of alu1bit is
constant delay: Time := 10 ns;
begin
process (a,b,c_in,opcode)
variable p: std_logic;
variable g: std_logic;
begin
p := (a and b);
g := (a xor b);
c_out <= (((not c_in) and b and a) or (c_in and (a or b))) after delay;
if(opcode = "00") then
result <= p after delay;
elsif(opcode = "01") then
result <= (a or b)after delay;
elsif(opcode = "10") then
result <= (((not c_in) and g) or (c_in and (not g))) after delay;
else
result <= 'X' after delay;
end if;
end process;
end Behavioral;
