info x 143 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic
col x 257 0 0 0 0 0 0 0 
radix x 2 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 alu1bit
term mark 66 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

var add 1 0 0 34 7 13 0 0 ainstd_logic
var add 2 0 0 34 8 13 0 0 binstd_logic
var add 3 0 0 34 9 16 0 0 c_ininstd_logic
var add 4 1 0 36 10 18 0 0 opcodeinstd_logic_vector
var add 5 31 0 34 11 18 0 0 resultoutstd_logic
var add 6 31 0 34 12 17 0 0 c_outoutstd_logic
vdone xxx 0 0 0 0 0 0 0 0 
npos xxx 102 0 0 0 0 0 0 0 
cell fill 1 0 0 0 0 0 0 0 0
cell fill 1 8 0 0 0 0 0 0 1
cell fill 1 16 0 0 0 0 0 0 0
cell fill 1 24 0 0 0 0 0 0 1
cell fill 1 32 0 0 0 0 0 0 0
cell fill 1 40 0 0 0 0 0 0 1
cell fill 1 48 0 0 0 0 0 0 0
cell fill 1 56 0 0 0 0 0 0 1
cell fill 1 64 0 0 0 0 0 0 0
cell fill 2 0 0 0 0 0 0 0 0
cell fill 2 4 0 0 0 0 0 0 1
cell fill 2 8 0 0 0 0 0 0 0
cell fill 2 12 0 0 0 0 0 0 1
cell fill 2 16 0 0 0 0 0 0 0
cell fill 2 20 0 0 0 0 0 0 1
cell fill 2 24 0 0 0 0 0 0 0
cell fill 2 28 0 0 0 0 0 0 1
cell fill 2 32 0 0 0 0 0 0 0
cell fill 2 36 0 0 0 0 0 0 1
cell fill 2 40 0 0 0 0 0 0 0
cell fill 2 44 0 0 0 0 0 0 1
cell fill 2 48 0 0 0 0 0 0 0
cell fill 2 52 0 0 0 0 0 0 1
cell fill 2 56 0 0 0 0 0 0 0
cell fill 2 60 0 0 0 0 0 0 1
cell fill 2 64 0 0 0 0 0 0 0
cell fill 3 0 0 0 0 0 0 0 0
cell fill 3 2 0 0 0 0 0 0 1
cell fill 3 4 0 0 0 0 0 0 0
cell fill 3 6 0 0 0 0 0 0 1
cell fill 3 8 0 0 0 0 0 0 0
cell fill 3 10 0 0 0 0 0 0 1
cell fill 3 12 0 0 0 0 0 0 0
cell fill 3 14 0 0 0 0 0 0 1
cell fill 3 16 0 0 0 0 0 0 0
cell fill 3 18 0 0 0 0 0 0 1
cell fill 3 20 0 0 0 0 0 0 0
cell fill 3 22 0 0 0 0 0 0 1
cell fill 3 24 0 0 0 0 0 0 0
cell fill 3 26 0 0 0 0 0 0 1
cell fill 3 28 0 0 0 0 0 0 0
cell fill 3 30 0 0 0 0 0 0 1
cell fill 3 32 0 0 0 0 0 0 0
cell fill 3 34 0 0 0 0 0 0 1
cell fill 3 36 0 0 0 0 0 0 0
cell fill 3 38 0 0 0 0 0 0 1
cell fill 3 40 0 0 0 0 0 0 0
cell fill 3 42 0 0 0 0 0 0 1
cell fill 3 44 0 0 0 0 0 0 0
cell fill 3 46 0 0 0 0 0 0 1
cell fill 3 48 0 0 0 0 0 0 0
cell fill 3 50 0 0 0 0 0 0 1
cell fill 3 52 0 0 0 0 0 0 0
cell fill 3 54 0 0 0 0 0 0 1
cell fill 3 56 0 0 0 0 0 0 0
cell fill 3 58 0 0 0 0 0 0 1
cell fill 3 60 0 0 0 0 0 0 0
cell fill 3 62 0 0 0 0 0 0 1
cell fill 3 64 0 0 0 0 0 0 0
cell fill 4 0 0 0 0 0 0 0 00
cell fill 4 16 0 0 0 0 0 0 01
cell fill 4 32 0 0 0 0 0 0 10
cell fill 4 48 0 0 0 0 0 0 11
time info 10 10 10 10 50 50 0 1 ns
font save -14 0 400 49 0 0 0 0 Times New Roman
src mod 0 1102466304 29657151 6 0 0 0 0 alu1bit.vhd
utd false 0 0 0 0 0 0 0 0 
cellenab on 0 0 0 0 0 0 0 0 
grid on 0 0 0 0 0 0 0 0 
com add 1 2 10 40 8 0 -67 0 Waveform created by
HDL Bencher 4.1i
Source = alu1bit.vhd
Sun Aug 15 16:57:40 2004
type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 7 0 0 0 0 0 0 0 memvVECTORDOWNTO
type info 7 0 0 0 0 0 0 0 qqBITDOWNTO
type info 7 0 0 0 0 0 0 0 std_logicBITDOWNTO
type info 7 0 0 0 0 0 0 0 STD_ULOGICBITDOWNTO
type info 7 0 0 0 0 0 0 0 bitBITDOWNTO
type info 7 0 0 0 0 0 0 0 1BITDOWNTO
type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO
type info -2147483647 2147483647 0 0 0 0 0 0 integerINTEGERTO
type info 3 0 0 0 0 0 0 0 sizeVECTORDOWNTO
type info 2 0 0 0 0 0 0 0 mybyteVECTORDOWNTO
type info 2 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO
type info 31 0 0 0 0 0 0 0 bit_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 UnsignedVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 machine_cycle_statesBITDOWNTO
type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 STD_ULOGIC_VECTORVECTORDOWNTO
val info 1 0 0 0 0 0 0 0 `C_NOP7
val info 1 0 0 0 0 0 0 0 `C_REFRSH1
val info 1 0 0 0 0 0 0 0 `s22
val info 1 0 0 0 0 0 0 0 `state_delay6
val info 1 0 0 0 0 0 0 0 `s33
val info 1 0 0 0 0 0 0 0 `FWIDTH32
val info 1 0 0 0 0 0 0 0 `s00
val info 1 0 0 0 0 0 0 0 `IF01
val info 0 0 0 0 0 0 0 0 440
val info 1 0 0 0 0 0 0 0 `D10
val info 0 0 0 0 0 0 0 0 c_signed0
val info 0 0 0 0 0 0 0 0 c_clear0
val info 0 0 0 0 0 0 0 0 12
val info 1 0 0 0 0 0 0 0 `BR00
val info 1 0 0 0 0 0 0 0 `s44
val info 1 0 0 0 0 0 0 0 `RES5
val info 1 0 0 0 0 0 0 0 `FCWIDTH2
val info 1 0 0 0 0 0 0 0 `TCKO0
val info 1 0 0 0 0 0 0 0 `IF23
val info 0 0 0 0 0 0 0 0 c_no_override0
val info 0 0 0 0 0 0 0 0 numaddr3
val info 1 0 0 0 0 0 0 0 `IF12
val info 1 0 0 0 0 0 0 0 `OD4
val info 1 0 0 0 0 0 0 0 `N5
val info 1 0 0 0 0 0 0 0 `FDEPTH4
val info 0 0 0 0 0 0 0 0 c_add0
val info 1 0 0 0 0 0 0 0 `F_DEASSERT4
val info 1 0 0 0 0 0 0 0 `s11
val info 0 0 0 0 0 0 0 0 c_reg0
val info 1 0 0 0 0 0 0 0 `Q25
val info 0 0 0 0 0 0 0 0 width4
val info 1 0 0 0 0 0 0 0 `C_READ5
val info 1 0 0 0 0 0 0 0 `C_WRITE4
val info 1 0 0 0 0 0 0 0 `C_P_CHRG2
val info 1 0 0 0 0 0 0 0 `C_ACTIVE3
val info 1 0 0 0 0 0 0 0 `C_L_MODE0
val info 1 0 0 0 0 0 0 0 `F_IDLE1
val info 1 0 0 0 0 0 0 0 `F_ASSERT2
val info 0 0 0 0 0 0 0 0 c_unsigned0
val info 0 0 0 0 0 0 0 0 c_override0
opt vhdl87 0 0 0 0 0 0 0 0 
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function generateHref(atag, template){
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var tripod_ratings_hash = "1417984531:e4ebfd1589af6303d86b225ca88c89da";

var lycos_ad_category = null;

var lycos_ad_remote_addr = "192.99.32.115";
var lycos_ad_www_server = "www.tripod.lycos.com";
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