library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic_vector(3 downto 0);
c_out : out std_logic);
end alu4bit;
architecture structural of alu4bit is
component alu1bit is
Port ( a : in std_logic;
b : in std_logic;
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic;
c_out : out std_logic);
end component;
signal c1, c2, c3 : std_logic;
begin
ALU1: alu1bit port map(a(0), b(0), c_in, opcode, result(0), c1);
ALU2: alu1bit port map(a(1), b(1), c1, opcode, result(1), c2);
ALU3: alu1bit port map(a(2), b(2), c2, opcode, result(2), c3);
ALU4: alu1bit port map(a(3), b(3), c3, opcode, result(3), c_out);
end structural;
