info x 109 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic col x 257 0 0 0 0 0 0 0 radix x 2 0 0 0 0 0 0 0 entity name 0 0 0 0 0 0 0 0 alu4bit term mark 30 0 0 0 0 0 0 0 vlib save 0 0 0 0 0 0 0 0 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; var add 1 3 0 36 10 9 0 0 ainstd_logic_vector var add 2 3 0 36 11 13 0 0 binstd_logic_vector var add 3 31 0 34 12 16 0 0 c_ininstd_logic var add 4 1 0 36 13 18 0 0 opcodeinstd_logic_vector var add 5 3 0 36 14 18 0 0 resultoutstd_logic_vector var add 6 31 0 34 15 17 0 0 c_outoutstd_logic vdone xxx 0 0 0 0 0 0 0 0 npos xxx 102 0 0 0 0 0 0 0 cell fill 1 0 0 0 0 0 0 0 0000 cell fill 1 2 0 0 0 0 0 0 0001 cell fill 1 4 0 0 0 0 0 0 0010 cell fill 1 6 0 0 0 0 0 0 1111 cell fill 1 8 0 0 0 0 0 0 0100 cell fill 1 10 0 0 0 0 0 0 0000 cell fill 1 12 0 0 0 0 0 0 0000 cell fill 1 14 0 0 0 0 0 0 0001 cell fill 1 16 0 0 0 0 0 0 1111 cell fill 1 18 0 0 0 0 0 0 0011 cell fill 1 20 0 0 0 0 0 0 0100 cell fill 1 22 0 0 0 0 0 0 0101 cell fill 1 24 0 0 0 0 0 0 0110 cell fill 1 26 0 0 0 0 0 0 0111 cell fill 1 28 0 0 0 0 0 0 0000 cell fill 2 0 0 0 0 0 0 0 0100 cell fill 2 2 0 0 0 0 0 0 0011 cell fill 2 4 0 0 0 0 0 0 0010 cell fill 2 6 0 0 0 0 0 0 1111 cell fill 2 8 0 0 0 0 0 0 0000 cell fill 2 12 0 0 0 0 0 0 0100 cell fill 2 14 0 0 0 0 0 0 0011 cell fill 2 16 0 0 0 0 0 0 1111 cell fill 2 18 0 0 0 0 0 0 0001 cell fill 2 20 0 0 0 0 0 0 0000 cell fill 2 28 0 0 0 0 0 0 0000 cell fill 3 0 0 0 0 0 0 0 0 cell fill 3 12 0 0 0 0 0 0 1 cell fill 4 0 0 0 0 0 0 0 10 time info 50 50 10 10 50 50 0 1 ns font save -14 0 400 49 0 0 0 0 Times New Roman src mod 0 4232793344 29657161 0 0 0 0 0 alu4bit.vhd utd false 0 0 0 0 0 0 0 0 cellenab on 0 0 0 0 0 0 0 0 grid on 0 0 0 0 0 0 0 0 com add 1 0 50 202 8 0 -67 0 Waveform created by HDL Bencher 4.1i Source = alu4bit.vhd Sun Aug 22 17:33:30 2004 type info 3 0 0 0 0 0 0 0 sizeVECTORDOWNTO type info 31 0 0 0 0 0 0 0 bit_vectorVECTORDOWNTO type info 31 0 0 0 0 0 0 0 machine_cycle_statesBITDOWNTO type info 31 0 0 0 0 0 0 0 STD_ULOGICBITDOWNTO type info 31 0 0 0 0 0 0 0 qqBITDOWNTO type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO type info 31 0 0 0 0 0 0 0 1BITDOWNTO type info 7 0 0 0 0 0 0 0 memvVECTORDOWNTO type info 7 0 0 0 0 0 0 0 std_logicBITDOWNTO type info 7 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO type info 31 0 0 0 0 0 0 0 UnsignedVECTORDOWNTO type info 31 0 0 0 0 0 0 0 logic_vectorVECTORDOWNTO type info -2147483647 2147483647 0 0 0 0 0 0 integerINTEGERTO type info 2 0 0 0 0 0 0 0 mybyteVECTORDOWNTO type info 2 0 0 0 0 0 0 0 bitBITDOWNTO type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO type info 31 0 0 0 0 0 0 0 STD_ULOGIC_VECTORVECTORDOWNTO val info 0 0 0 0 0 0 0 0 c_signed0 val info 0 0 0 0 0 0 0 0 c_clear0 val info 0 0 0 0 0 0 0 0 12 val info 1 0 0 0 0 0 0 0 `BR00 val info 1 0 0 0 0 0 0 0 `s44 val info 1 0 0 0 0 0 0 0 `RES5 val info 1 0 0 0 0 0 0 0 `FCWIDTH2 val info 1 0 0 0 0 0 0 0 `TCKO0 val info 1 0 0 0 0 0 0 0 `IF23 val info 0 0 0 0 0 0 0 0 c_no_override0 val info 0 0 0 0 0 0 0 0 numaddr3 val info 1 0 0 0 0 0 0 0 `IF12 val info 1 0 0 0 0 0 0 0 `OD4 val info 1 0 0 0 0 0 0 0 `N5 val info 1 0 0 0 0 0 0 0 `FDEPTH4 val info 0 0 0 0 0 0 0 0 c_add0 val info 1 0 0 0 0 0 0 0 `F_DEASSERT4 val info 1 0 0 0 0 0 0 0 `s11 val info 0 0 0 0 0 0 0 0 c_reg0 val info 1 0 0 0 0 0 0 0 `Q25 val info 0 0 0 0 0 0 0 0 width4 val info 1 0 0 0 0 0 0 0 `C_READ5 val info 1 0 0 0 0 0 0 0 `C_WRITE4 val info 1 0 0 0 0 0 0 0 `C_P_CHRG2 val info 1 0 0 0 0 0 0 0 `C_ACTIVE3 val info 1 0 0 0 0 0 0 0 `C_L_MODE0 val info 1 0 0 0 0 0 0 0 `F_IDLE1 val info 1 0 0 0 0 0 0 0 `F_ASSERT2 val info 0 0 0 0 0 0 0 0 c_unsigned0 val info 1 0 0 0 0 0 0 0 `C_NOP7 val info 1 0 0 0 0 0 0 0 `C_REFRSH1 val info 1 0 0 0 0 0 0 0 `s22 val info 1 0 0 0 0 0 0 0 `state_delay6 val info 1 0 0 0 0 0 0 0 `s33 val info 1 0 0 0 0 0 0 0 `FWIDTH32 val info 1 0 0 0 0 0 0 0 `s00 val info 1 0 0 0 0 0 0 0 `IF01 val info 0 0 0 0 0 0 0 0 440 val info 1 0 0 0 0 0 0 0 `D10 val info 0 0 0 0 0 0 0 0 c_override0 opt vhdl87 0 0 0 0 0 0 0 0