library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu8bit is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
c_out : out std_logic);
end alu8bit;
architecture structural of alu8bit is
component alu4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic_vector(3 downto 0);
c_out : out std_logic);
end component;
signal c1 : std_logic;
begin
ALU1: alu4bit port map(a(3 downto 0), b(3 downto 0), c_in, opcode, result(3 downto 0), c1);
ALU2: alu4bit port map(a(7 downto 4), b(7 downto 4), c1, opcode, result(7 downto 4), c_out);
end structural;
