library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu_8bit is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
c_out : out std_logic);
end alu_8bit;
architecture Behavioral of alu_8bit is
constant delay: Time := 8 * 10 ns;
begin
process (a,b,c_in,opcode)
variable p,g,c,sum: std_logic_vector(7 downto 0);
begin
p := (a and b);
c(0) := (((not c_in) and b(0) and a(0)) or (c_in and (a(0) or b(0))));
for I in 1 to 7 loop
c(I) := (((not c(I-1)) and b(I) and a(I)) or (c(I-1) and (a(I) or b(I))));
end loop;
c_out <= c(7) after delay;
g := (a xor b);
sum(0) := (((not c_in) and g(0)) or (c_in and (not g(0))));
for I in 1 to 7 loop
sum(I) := (((not c(I-1)) and g(I)) or (c(I-1) and (not g(I))));
end loop;
case opcode is
when "00" =>
result <= p after delay;
when "01" =>
result <= (a or b) after delay;
when "10" =>
result <= sum after delay;
when others =>
result <= "XXXXXXXX" after delay;
end case;
end process;
end Behavioral;
