info x 151 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic col x 257 0 0 0 0 0 0 0  radix x 10 0 0 0 0 0 0 0  entity name 0 0 0 0 0 0 0 0 alu_8bit term mark 64 0 0 0 0 0 0 0  vlib save 0 0 0 0 0 0 0 0 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;  var add 1 7 0 36 7 13 0 0 ainstd_logic_vector var add 2 7 0 36 8 13 0 0 binstd_logic_vector var add 3 31 0 34 9 16 0 0 c_ininstd_logic var add 4 1 0 36 10 18 0 0 opcodeinstd_logic_vector var add 5 7 0 36 11 18 0 0 resultoutstd_logic_vector var add 6 31 0 34 12 17 0 0 c_outoutstd_logic vdone xxx 0 0 0 0 0 0 0 0  npos xxx 106 0 0 0 0 0 0 0  cell fill 1 0 0 0 0 0 0 0 00000000 cell fill 1 2 0 0 0 0 0 0 10001001 cell fill 1 4 0 0 0 0 0 0 00000000 cell fill 1 6 0 0 0 0 0 0 10001011 cell fill 1 8 0 0 0 0 0 0 00000000 cell fill 1 10 0 0 0 0 0 0 10010110 cell fill 1 12 0 0 0 0 0 0 00000000 cell fill 1 14 0 0 0 0 0 0 01000100 cell fill 1 16 0 0 0 0 0 0 00000000 cell fill 1 18 0 0 0 0 0 0 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0 0 0 cell fill 3 56 0 0 0 0 0 0 1 cell fill 4 0 0 0 0 0 0 0 00 cell fill 4 16 0 0 0 0 0 0 01 cell fill 4 32 0 0 0 0 0 0 10 cell fill 4 48 0 0 0 0 0 0 11 time info 50 50 10 10 50 50 0 1 ns font save -14 0 400 49 0 0 0 0 Times New Roman src mod 0 4073662208 29657952 0 0 0 0 0 alu_8bit.vhd utd false 0 0 0 0 0 0 0 0  cellenab on 0 0 0 0 0 0 0 0  grid on 0 0 0 0 0 0 0 0  com add 1 4 10 160 8 0 -67 0 Waveform created by HDL Bencher 4.1i Source = alu_8bit.vhd Sun Aug 22 20:33:19 2004 type info 0 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO type info 0 0 0 0 0 0 0 0 STD_ULOGICBITDOWNTO type info 0 0 0 0 0 0 0 0 1BITDOWNTO type info 0 0 0 0 0 0 0 0 bitBITDOWNTO type info 0 0 0 0 0 0 0 0 std_logicBITDOWNTO type info 31 0 0 0 0 0 0 0 logic_vectorVECTORDOWNTO type info 7 0 0 0 0 0 0 0 memvVECTORDOWNTO type info 7 0 0 0 0 0 0 0 qqBITDOWNTO type info 2 0 0 0 0 0 0 0 mybyteVECTORDOWNTO type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO type info -2147483647 2147483647 0 0 0 0 0 0 integerINTEGERTO type info 31 0 0 0 0 0 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