library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IFU is
Port ( instIN : in std_logic_vector(7 downto 0);
pc: in std_logic_vector(7 downto 0);
CLK : in std_logic;
RESET : in std_logic;
BraSat : in std_logic;
instOUT : out std_logic_vector(7 downto 0));
end IFU;
architecture Structural of IFU is
component alu_8bit is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c_in : in std_logic;
opcode : in std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
c_out : out std_logic);
end component;
component signExtend is
Port ( inst : in std_logic_vector(3 downto 0);
extend : out std_logic_vector(7 downto 0));
end component;
component mux2X8Bit is
Port ( left : in std_logic_vector(7 downto 0);
right : in std_logic_vector(7 downto 0);
braSat : in std_logic;
inst4 : in std_logic;
output : out std_logic_vector(7 downto 0));
end component;
component memory is
Port ( address : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0));
end component;
signal pc1 : std_logic_vector(7 downto 0);
signal pc2 : std_logic_vector(7 downto 0);
signal c1 : std_logic;
signal c2 : std_logic;
signal extend : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
signal address : std_logic_vector(7 downto 0);
begin
ALU1: alu_8bit port map(pc, X"01", '0', "10", pc1, c1);
SIGN: signExtend port map (instIN(3 downto 0), extend);
ALU2: alu_8bit port map(pc1, extend, c1, "10", pc2, c2);
MUX: mux2X8Bit port map(pc2, pc1, BraSat, instIN(4), output);
process(CLK, RESET, output)
begin
if(RESET = '1') then
address <= X"00";
elsif(CLK ='1') then
address <= output;
end if;
end process;
MEM: memory port map(address,instOUT);
end Structural;
