info x 118 201 0 0 0 0 0 0 VHDLvhdl_genericverilog_generic col x 257 0 0 0 0 0 0 0  radix x 2 0 0 0 0 0 0 0  entity name 0 0 0 0 0 0 0 0 IFU term mark 63 0 0 0 0 0 0 0  vlib save 0 0 0 0 0 0 0 0 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;  var add 3 31 0 226 9 15 0 0 CLKinstd_logic var add 1 7 0 36 7 18 0 0 instINinstd_logic_vector var add 2 7 0 36 8 15 0 0 pcinstd_logic_vector var add 4 31 0 34 10 17 0 0 RESETinstd_logic var add 5 31 0 34 11 18 0 0 BraSatinstd_logic var add 6 7 0 36 12 19 0 0 instOUToutstd_logic_vector vdone xxx 0 0 0 0 0 0 0 0  npos xxx 108 0 0 0 0 0 0 0  cell fill 2 0 0 0 0 0 0 0 00000000 cell fill 2 4 0 0 0 0 0 0 00011111 cell fill 2 8 0 0 0 0 0 0 00001111 cell fill 2 12 0 0 0 0 0 0 00010001 cell fill 2 16 0 0 0 0 0 0 00000001 cell fill 2 20 0 0 0 0 0 0 00010101 cell fill 2 24 0 0 0 0 0 0 00000010 cell fill 2 28 0 0 0 0 0 0 00010010 cell fill 2 32 0 0 0 0 0 0 00000100 cell fill 2 36 0 0 0 0 0 0 00011011 cell fill 2 40 0 0 0 0 0 0 00000101 cell fill 2 44 0 0 0 0 0 0 00011100 cell fill 2 48 0 0 0 0 0 0 00000001 cell fill 2 52 0 0 0 0 0 0 00010001 cell fill 2 56 0 0 0 0 0 0 00000011 cell fill 2 60 0 0 0 0 0 0 00010011 cell fill 3 0 0 0 0 0 0 0 00000000 cell fill 3 4 0 0 0 0 0 0 00000000 cell fill 3 8 0 0 0 0 0 0 00000010 cell fill 3 12 0 0 0 0 0 0 00000011 cell fill 3 16 0 0 0 0 0 0 00000000 cell fill 3 20 0 0 0 0 0 0 00000000 cell fill 3 24 0 0 0 0 0 0 00000110 cell fill 3 28 0 0 0 0 0 0 00000111 cell fill 3 32 0 0 0 0 0 0 00000010 cell fill 3 36 0 0 0 0 0 0 00000011 cell fill 3 40 0 0 0 0 0 0 00000100 cell fill 3 44 0 0 0 0 0 0 00000101 cell fill 3 48 0 0 0 0 0 0 00000110 cell fill 3 52 0 0 0 0 0 0 00000111 cell fill 3 56 0 0 0 0 0 0 00001000 cell fill 3 60 0 0 0 0 0 0 00001001 cell fill 4 0 0 0 0 0 0 0 0 cell fill 4 32 0 0 0 0 0 0 1 cell fill 5 0 0 0 0 0 0 0 0 cell fill 5 16 0 0 0 0 0 0 1 cell fill 5 32 0 0 0 0 0 0 0 cell fill 5 44 0 0 0 0 0 0 1 time info 50 50 10 10 50 50 1 1 nsCLK font save -14 0 400 49 0 0 0 0 Times New Roman src mod 0 3721770496 29660799 0 0 0 0 0 IFU.vhd utd false 0 0 0 0 0 0 0 0  cellenab on 0 0 0 0 0 0 0 0  grid on 0 0 0 0 0 0 0 0  com add 1 0 10 160 8 0 -67 0 Waveform created by HDL Bencher 4.1i Source = IFU.vhd Thu Sep 09 19:03:28 2004 type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO type info 31 0 0 0 0 0 0 0 std_logicBITDOWNTO type info 31 0 0 0 0 0 0 0 vlbit_1dBITDOWNTO type info 31 0 0 0 0 0 0 0 qqBITDOWNTO type info 31 0 0 0 0 0 0 0 machine_cycle_statesBITDOWNTO type info 31 0 2 0 0 0 0 0 byteVECTORDOWNTO type info 31 0 0 0 0 0 0 0 bit_vectorVECTORDOWNTO type info -2147483647 2147483647 0 0 0 0 0 0 integerINTEGERTO type info -2147483647 2147483647 0 0 0 0 0 0 1BITTO type info 31 0 0 0 0 0 0 0 logic_vectorVECTORDOWNTO type info 7 0 0 0 0 0 0 0 memvVECTORDOWNTO type info 7 0 0 0 0 0 0 0 STD_ULOGICBITDOWNTO type info 3 0 0 0 0 0 0 0 sizeVECTORDOWNTO type info 31 0 0 0 0 0 0 0 UnsignedVECTORDOWNTO type info 2 0 0 0 0 0 0 0 mybyteVECTORDOWNTO type info 2 0 0 0 0 0 0 0 bitBITDOWNTO type info 31 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO type info 31 0 0 0 0 0 0 0 STD_ULOGIC_VECTORVECTORDOWNTO val info 0 0 0 0 0 0 0 0 width4 val info 1 0 0 0 0 0 0 0 `C_READ5 val info 1 0 0 0 0 0 0 0 `C_WRITE4 val info 1 0 0 0 0 0 0 0 `C_P_CHRG2 val info 1 0 0 0 0 0 0 0 `C_ACTIVE3 val info 1 0 0 0 0 0 0 0 `C_L_MODE0 val info 1 0 0 0 0 0 0 0 `F_IDLE1 val info 1 0 0 0 0 0 0 0 `F_ASSERT2 val info 0 0 0 0 0 0 0 0 c_unsigned0 val info 1 0 0 0 0 0 0 0 `C_NOP7 val info 1 0 0 0 0 0 0 0 `C_REFRSH1 val info 1 0 0 0 0 0 0 0 `s22 val info 1 0 0 0 0 0 0 0 `state_delay6 val info 1 0 0 0 0 0 0 0 `s33 val info 1 0 0 0 0 0 0 0 `FWIDTH32 val info 1 0 0 0 0 0 0 0 `s00 val info 1 0 0 0 0 0 0 0 `IF01 val info 0 0 0 0 0 0 0 0 440 val info 1 0 0 0 0 0 0 0 `D10 val info 0 0 0 0 0 0 0 0 c_signed0 val info 0 0 0 0 0 0 0 0 c_clear0 val info 0 0 0 0 0 0 0 0 12 val info 1 0 0 0 0 0 0 0 `BR00 val info 1 0 0 0 0 0 0 0 `s44 val info 1 0 0 0 0 0 0 0 `RES5 val info 1 0 0 0 0 0 0 0 `FCWIDTH2 val info 1 0 0 0 0 0 0 0 `TCKO0 val info 1 0 0 0 0 0 0 0 `IF23 val info 0 0 0 0 0 0 0 0 c_no_override0 val info 0 0 0 0 0 0 0 0 numaddr3 val info 1 0 0 0 0 0 0 0 `IF12 val info 1 0 0 0 0 0 0 0 `OD4 val info 1 0 0 0 0 0 0 0 `N5 val info 1 0 0 0 0 0 0 0 `FDEPTH4 val info 0 0 0 0 0 0 0 0 c_add0 val info 1 0 0 0 0 0 0 0 `F_DEASSERT4 val info 1 0 0 0 0 0 0 0 `s11 val info 0 0 0 0 0 0 0 0 c_reg0 val info 1 0 0 0 0 0 0 0 `Q25 val info 0 0 0 0 0 0 0 0 c_override0 opt vhdl87 0 0 0 0 0 0 0 0 
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