library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity memory is Port ( address : in std_logic_vector(7 downto 0); read_data : out std_logic_vector(7 downto 0)); end memory; architecture Behavioral of memory is type mem_array is array(0 to 31) of std_logic_vector(7 downto 0); begin process(address) variable data_mem: mem_array := ( X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13", X"14", X"15", X"16", X"17", X"18", X"19", X"1A", X"1B", X"1C", X"1D", X"1E", X"1F"); variable addr: integer; begin addr:=conv_integer(address(4 downto 0)); read_data <= data_mem(addr); end process; end Behavioral;
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