library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2X8Bit is
Port ( left : in std_logic_vector(7 downto 0);
right : in std_logic_vector(7 downto 0);
braSat : in std_logic;
inst4 : in std_logic;
output : out std_logic_vector(7 downto 0));
end mux2X8Bit;
architecture Behavioral of mux2X8Bit is
begin
process(left,right,braSat,inst4)
variable option : std_logic;
begin
option := inst4 and braSat;
if(option = '1') then
output <= left;
else
output <= right;
end if;
end process;
end Behavioral;
