library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity signExtend is
Port ( inst : in std_logic_vector(3 downto 0);
extend : out std_logic_vector(7 downto 0));
end signExtend;
architecture Behavioral of signExtend is
begin
process(inst)
begin
extend(3 downto 0) <= inst(3 downto 0);
if(inst(3) = '1') then
extend(7 downto 4) <= "1111";
else
extend(7 downto 4) <= "0000";
end if;
end process;
end Behavioral;
