JDF E
// Created by ISE ver 1.0
PROJECT wk06
DESIGN wk06 Normal
DEVKIT xcv50-6bg256
DEVFAM virtex
FLOW XST VHDL
STIMULUS ifu_tbw.tbw Normal
STIMULUS mux2X8Bit_tbw.tbw Normal
STIMULUS signExtend_tbw.tbw Normal
STIMULUS memory_tbw.tbw Normal
MODULE alu_8bit.vhd
MODSTYLE alu_8bit Normal
MODULE IFU.vhd
MODSTYLE ifu Normal
MODULE memory.vhd
MODSTYLE memory Normal
MODULE signExtend.vhd
MODSTYLE signextend Normal
MODULE mux2X8Bit.vhd
MODSTYLE mux2x8bit Normal
[STRATEGY-LIST]
Normal=True, 1093780897
[Normal]
p_ModelSimSimRunTime=xstvhd, VIRTEX, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1093781396, 2000ns
