COMP3211/9211 04s2 Tutorial 4 (Weeks 08 & 09)
---------------------------------------------

The selection of tutorial questions is chosen to provide coverage of
topics relevant to this Session's presentation.

There are many more questions listed than it is possible to cover during
the tutorial hour. I will therefore label them as W = warmup exercise
(simple exercises that you should be able to do without coaching or
assistance - I would recommend you try these before the class); D =
discuss (these questions are prime candidates for further discussion -
you should prepare for these before the class); and F = followup (you
should attempt these as soon as possible after the tutorial class to
practice your skills, and get a different insight into tutorial questions
covered in class). Exam questions are more likely to be similar in style
to D and F type questions.

Key: SRQ = Stallings, Review Question; SP = Stallings Problem; P = Patterson &
     Hennessy Exercise (Note you will in general need to source the P problems
     in a copy of the Second Edition); Y = Yalamanchili


Hand-in Exercises
-----------------

These exercises will be marked and contribute to your final assessment
in the course.

Q00. If your student number is odd, prepare an answer to Q01, and be
     ready to present your answer at the front of the class at the
     beginning of your tutorial.

     If your student number is even, prepare an answer to Q02, and be
     ready to present your answer at the front of the class at the
     beginning of your tutorial.

     In either case, hand in your answer to your tutor at the start of 
     the class.



Warmup Exercises
----------------

Q01. Assume that the operation times for the major functional units used in a
     processor design are the following:

        memory read: 2 ns
        memory write: 3 ns
        ALU: 2 ns
        Adder: 2 ns
        Decoder: 1ns
        register file (read or write): 2 ns
        Others: 0 ns

        1. Determine the clock cycle time if it is designed as a single cycle 
           processor.

        2. Determine the clock cycle time if it is designed as a 5 stage 
           multicycle processor. Draw a high level block diagram of the 
           multicycle datapath

        3. For an application with instruction mix: 20% load, 10% store, 
           5% jump and 65% R-type, what is the CPI for each design? 


Q02. [P&H 6.5, modified] For each pipeline register in Slide 8 of Lecture 11,
     label each portion of the pipeline register with the name of the 
     value that is loaded into the register. Determine the length of 
     each field in bits. For example, the IF/ID pipeline register
     contains two fields, one of which is an instruction field that is
     32 bits wide.


Discussion Questions
--------------------

Q03. [P&H 5.21, modified] We wish to add support for four-operand arithmetic 
     instructions such as add3, which adds three numbers together
     instead of two:

        add3 $t5, $t6, $t7, $t8  # $t5 = $t6 + $t7 + $t8

     to the multicycle datapath discussed in Lecture 9. Assume that the
     ISA is modified by introducing a new instruction format similar
     to the R-format except that bits [4 - 0] are used to specify the
     additional register (we still use rs, rt, and rd) and of course
     a new opcode is used. Specify the microprogram necessary to
     process the instruction assuming a similar arrangement to Slides 
     35 - 37. Your solution should not rely on adding additional
     read ports to the register file, nor should a new ALU be used.


Q04. [P&H 6.3] How could we modify the following code to make use 
     of a delayed branch slot?

	LOOP:	lw	$2,	100($3)
		addi 	$3,	$3,	4
		beq	$3,	$4,	Loop


Q05. [P&H 6.9] {P&H 6.13 in 3rd Ed}


Follow-up Questions
-------------------

Q06. [P&H 5.24] {This problem is similar but not identical to P&H 5.36
     in the 3rd Ed}