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Department of Electronic Science

Fergusson College, Pune 4

Class XI (Practical Sheet)

Expt No.

Title FET Characteristics

Aim: To study drain and transfer characteristics of EFT.


The EFT is a high input impedance devices (Ri = 10 t0 100MW ). The FET is a voltage controlled device, and not current controlled like a conventional transistor. It shows a high degree of isolation between input and output. The present experiment is deviced by keeping following objectives in mind.


  1. To determine and plot the family of drain characteristics of a JFET.
  2. To determine the effect of drain to source voltage VDS on drain current ID.
  3. To determine and plot a JFET transfer curve, ID versus VGS, for a specified value of VDS.
  4. To calculate the parameters such as gm, Idss, Vp etc.

Theoretical Background:

The field effect transistor is the solid state analogue of the triode valve. FETS are unipolar devices because their action depends on only one type of charge carrier. There are two types of FETS: the junction type (JFET) and the metal oxide semiconductor type (MOSFET).

JFET consists of a bar of n-type or p-type semiconductor with ohmic contacts at the two ends. One end is called the source (S); the other, the drain (D). The bar acts as a simple resistor. A region of oppositely doped semiconducting material diffused around the bar constitutes the third electrode called the gate (G).

The schematic representation of an N-channel FET is shown in Fig. 18.1. When gates 1 and 2 are internally connected in the manufacturing process, the device is a single gate FET. When separate leads are brought out at each junction, a dual gate FET results.

In the FET the drain corresponds to the collector of BJT, the source to the emitter, and the gate to the base. However, the operation of this unipolar transistor is completely different from a bipolar transistor. The unipolar transistor is completely different from a bipolar transistor. The main operational difference is that drain current (ID) in the JFET is controlled by gate to source voltage (VGS), whereas collector current in bipolar transistor is controlled by base current.

To understand the operation of a JFET, consider the N-channel semiconductor with ohimc contacts at the top (drain) and the bottom (source) of the channel. If a battery VDD is connected across the channel, with the polarity positive to drain and negative polarity to source. Electrons from the negative terminal of the battery move through the source to N channel to replace those that left at the drain. The effective way to control the drain current is to reverse bias the gate with respect to the source as shown in fig. 18.2. By reverse biasing the gate, the electric field at the junction has effect of widening the gate, further reducing the channel width. If the negative bias is increased sufficiently, the gate becomes so wide that the channel is blocked and no drain current flows.

The FET we have been discussing is an N channel, P gate device whose symbol is shown in Fig. 18.3. (a). Observe that the gate arrow points towards the N channel (vertical line, Similarly, in the arrow points away from the channel as shown in figure 18.3 (b). For a P-channel as shown in figure. For a P-channel FET, all battery polarities VGG and VDD must be reversed in connecting the FET in a circuit.

Designing/Component Selection:

Let us choose BFW 10 JFET as an example and design a circuit to study characteristics of it. BFW 10 to is a N-channel silicon FET. The absolute maximum ratings that we shall be required to use are listed below. These, in no case, are to be exceeded or even approached.

Maximum drain to source voltage (VDSmax) = 30V

Maximum gate to source voltage (open drain) = -VGSOmax = 30V

Maximum drain current = IDmax = 30 mA.

Total power dissipation at 250C = 300 mW.

The absolute maximum ratings of BFW 10 suggest that required voltage sources can be chosen to have following ratings

VGG = - 0 to 5V VDD = 0 to 10V

List of Components:





BFW 10


List of Test and Measuring Instruments:




Dual CVCC p/s voltmeters






0 5V

0 20V

0 25V

Test Procedure

  1. Drain Characteristics
  1. Connect the circuit as shown in figure 18.4.
  2. Set the output of variable dc power supply (VGG) so that gate to source voltage VGS = 0V.
  3. For this value of VGS, set VDS = 0 by adjusting variable dc power supply (VDD). Record the value of drain current (ID).
  4. Vary the value of VDS in step of 1 volt and record the corresponding value of ID.
  5. Repeat this procedure for three to four different values of VGS till ID cut off is reached.
  6. Plot the curves ID versus VDS for all values of VGS on a single graph paper.
  7. Determine IDSS and VP from these curves.
  1. Transfer Characteristics:
  1. Connect the circuit as shown in figure 18.4.
  2. Set the variable dc supply (VDD), so that the drain to source (VDS) = 5V.
  3. For this value of VDS, vary VGS in suitable steps and record corresponding values of drain currents (ID).
  4. Plot the curve of ID versus VGS.
  5. Determine the slope. Thus gm =

Observation Tables:

  1. Drain Characteristics:
  2. Sr. No.

    VDS (volts)

    Drain Current (ID), mA


    VGS = 0V

    VGS = - ---V

    VGS = - ---V

    VGS = - --- V










  3. Transfer Characteristics:

Sr. No.

VDS = ---- V



ID (mA)











From the drain characteristics, determine IDSS. VP similarly from transfer characteristics determine gm. Verify VGS (OFF) = VP

Experimental Report:

To be prepared by the student and should include the following.

  1. Comments on the nature of curves.
  2. Results and discussion.
  3. Problems encountered (if any).
  4. Definitions of some terms.
  5. Functioning of the circuit.
  6. Applications.