1.  Master-Slave JK Flip-Flop

     Modify the circuit diagram for the Master Slave (MS) JK Flip-flop
     (FF) in Figure A.61 in your text AS CORRECTED IN CLASS to
     incorporate a Clear Input.  Clear is independent of the clocks.
     When Clear is one it causes both Q of the master and Q of the
     slave to be set to 0.  Most FF's also have a Preset input, which
     causes both Q of the Master and Q of the slave to go to one
     when Preset is 1.  Label J, K, Clock, Clear, Q_m, Q'_m, Q_s,
     and Q'_s.  Use a logic simulator to implement the circuit and verify that all of
     the inputs work correctly.  Submit both the circuit diagram and
     timing diagram produced by the simulator.

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