Note to Undergraduate students:  You will have to register for BOTH CS 384.1 AND CS 384.3. This is necessary because the Department is unable to list a course for 4 credits.  It therefore had to list this course as 2 courses -- a 1 credit course and a 3 credit course.

1     Lecture:  Electrical properties of various families of digital and linear Integrated circuits and LEDs; RC circuits and pulse rise and fall time; triggering and timebases in oscilloscopes and logic analyzers; glitch detection and display.

        Laboratory:  Design and construction of a parity generator with LED display;  construction of a clock circuit with variable frequency and duty cycle; effect of stray capacitance; measurement of frequency, rise and fall times; measurement of power vs frequency in CMOS circuit; construction of ripple binary and decimal counter with seven segment display, use of a logic analyzer in both synchronous and asynchronous modes; glitch detection and triggering.

2     Lecture:  Architecture and instruction set of Intel 8086/88.  Instruction encoding,  Functions of the BIU and instruction queue; segment registers and general purpose registers; memory addressing modes.  IBM PC standard I/O port addresses, and addresses on the Royer (prototyping) board.

        Laboratory:  Use of MSDOS DEBUG to enter programs in HEX and ASM and to trace their execution; tracing the ROM BIOS reset sequence in the PC; Use of DEBUG for I/0 to the Royer Board.

3     Lecture:  Organization, programming, and interfacing of the Intel 8255; its uses in the IBM PC and on the Royer board, I/O address decoding on the Royer Board and In the IBM PC.

        Laboratory:  A program to generate a square wave using instruction timing to determine the frequency; turbo vs standard mode timing in the PC; A program to scan a hex keypad on the Royer board and to display the pressed key using the board's LEDs.

4     Lecture:  Interrupt processing in the 8086/88;  DOS and ROM BIOS software interrupts; The Intel 8259's organization, interfacing and programming; hardware interrupts in the PC and AT;  DEBUG'S use of interrupts and using DEBUG with interrupt handlers.

       Laboratory:  Examination of some ROM BIOS interrupt service routines (ISRs) and the interrupt vector table.  The keypad scan program is turned into an ISR for the 55 ms interrupt.  It is then made into a terminate and stay resident routine (TSR) and the 8255 and CPU are "time shared" by running the square wave program together with the TSR. Examination of the structure of the PSP under DOS.

5     Lecture:  Organization, programming, and interfacing of the Intel 8253;  uses of the 8253 in the PC.

        Laboratory:  Using the 8253 on the Royer board to time the inner and outer loops in the TSR;  Examination of a program that plays 3 part music using the Royer board's 8253 and speaker; using DEBUG to change the frequency of the PC's beep tone and to turn it on and off.

6      Lecture:  The IBM PC's use of the 8284, the generation of READY, and wait state calculations and generation.  MAX Mode of the 8086/88; the 8288, and the ISA bus.

         Laboratory:  A logic analyzer is used to analyze activity of the CPU during RESET.  The analyzer is triggered when a specific key is pressed on the Royer board's keypad while the TSR and square wave program are run.  All CPU activity is examined for instruction queue flushes.  The activity of LOCK is observed.  The logic analyzer is used to examine how DOS loads a program.

7       Lecture:  Organization, programming, and interfacing of the Intel 8251A; asynchronous serial communication.

          Laboratory:  An 8251A is interfaced to the Royer board using the boards 8253 as a baud rate generator and the 8255 to control the gating of the 8253, and a ISR is written for communications.  The serial output from the 8251A is connected to an AT's serial port and Kermit on the AT is used to communicate with the PC.

8        Lecture:  Organization, programming, and interfacing of the Intel 8237 DMA;  Dynamic RAM refresh, and the uses of the 8237 in the PC and AT.

           Laboratory:  The USART circuit constructed is modified so that output is controlled by the DMA without CPU intervention.  The program is modified to initialize the DMA.

9         Lecture:  Differences between members of the 86 family; designing a  system using an integrated chipset.