MC145158 PLL Integrated Circuits
The MC145158–2 has a fully programmable 14–bit reference counter, as well as fully programmable ÷ N and ÷ A counters. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered.
The MC145158–2 is an improved–performance drop–in replacement for the MC145158–1. Power consumption has decreased and ESD and latch–up performance have improved.
&127; Operating Temperature Range: – 40 to 85°C
&127; Low Power Consumption Through Use of CMOS Technology
&127; 3.0 to 9.0 V Supply Range
&127; Fully Programmable Reference and ÷ N Counters
&127;÷ R Range = 3 to 16383
&127;÷ N Range = 3 to 1023
&127; Dual Modulus Capability; ÷ A Range = 0 to 127
&127; f V and f R Outputs
&127; Lock Detect Signal
&127; Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
&127; “Linearized” Digital Phase Detector
&127; Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
&127; Chip Complexity: 6504 FETs or 1626 Equivalent Gates
Phase Loced Loop Software
Similar Packages
PIN DESCRIPTIONS
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on this input decrements the ÷ A and ÷ N counters. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV p–p. For larger ampli-tude signals (standard CMOS logic levels), dc coupling may be used.
Serial Data Inputs (Pins 9, 10)
to–high transition of the CLK shifts one bit of the on–chip shift registers. The last data bit entered which counter storage latch is activated; a logic 1 reference counter latch and a logic 0 selects the counter latch.
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-ter into the reference divider or ÷ N, ÷ A latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N, ÷ A latches are activated if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches.
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-nected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally–gener-ated reference signal. This signal is typically ac coupled to OSC in , but for larger amplitude signals (standard CMOS log-ic levels) dc coupling may also be used. In the external refer-ence mode, no connection is required to OSC out .
Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output produces a loop–error signal that is used with a loop filter to control a VCO.
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V
Frequency f V = f R and Phase Coincidence: High–Impedance State
Phase Detector B Outputs (Pins 16, 15)
Double–ended phase detector outputs. These outputs can be combined externally for a loop–error signal. A single– ended output is also available for this purpose (see PD out ). If frequency f V is greater than f R or if the phase of f V is leading, then error information is provided by fV pulsing low. fR remains essentially high. If the frequency f V is less than f R or if the phase of f V is lagging, then error information is provided by fR pulsing low. fV remains essentially high. If the frequency of f V = f R and both are in phase, then both fV and fR remain high except for a small minimum time period when both pulse low in phase.
Dual–Modulus Prescale Control Output (Pin 12)
This output generates a signal by the on–chip control logic circuitry for controlling an external dual–modulus prescaler. The MC level is low at the beginning of a count cycle and remains low until the ÷ A counter has counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N counter has counted the rest of the way down from its programmed value (N – A additional counts since both ÷ N and ÷ A are counting down during the first por-tion of the cycle). MC is then set back low, the counters pre-set to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (N T ) = N
Serial Data Input Method
Serial data is processed using three input pins (Data, Clock, and LE pins) to control the 15-bit reference divider and the 18-bit programmable divider separately.
Input binary-coded serial data to the Data pin.
Serial data is input to the internal shift register in sequence at the rise of each clock pulse. When the load enable signal input pin has a high level (or open), the input data is transferred to the latch depending on the control bit.
Control bit = “H”: Transfer to the 14-bit Reference Counter
Control bit = “L”: Transfer to the 14-bit Frequency Counter
Serial Data Input Timing
Divide Ratio of Reference Divider
The reference divider consists of a 14-bit shift register, a 14-bit latch, and a 14-bit reference counter. Serial data is made up of the following 15 bits:
Divide Ratio of Programmable Divider
The programmable divider consists of a 7-bit and 10-bit shift register, an 7-bit and 10-bit latch, and an 7-bit and 10-bit programmable counter. Serial data is made up of the following 18 bits:
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