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Following is the Pin File
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Library IEEE;
use IEEE.std_logic_1164.all;

Entity rn is
	port ( clk	: in   std_logic;
               reset : in  std_logic;
               qout : out  std_logic_vector(15 downto 0);
	       wr_data : out std_logic;
	       wr_data1 : out std_logic			
	     );
end rn;

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Following is the Arc File
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-- This is a 16 random number generator developed on 24 th April by Rajkumar. 
Library IEEE;
use IEEE.std_logic_1164.all;

Architecture A_rn of rn is
  signal qout_s : std_logic_vector(15 downto 0);
  signal tem_data : std_logic:='1';
begin
  qout <= qout_s;
  random_gen : process(clk)
    variable  temp : std_logic;
  begin
    if (reset = '1') then
      qout_s <= "1111111111111111";
    elsif (clk'event and clk  = '1') then
      temp := tem_data;
      wr_data <= temp;
      wr_data1 <= tem_data;
      temp := tem_data;	
      qout_s(0) <= qout_s(0) xor qout_s(15);

      for i in 15 downto 1 loop
      	qout_s(i) <= qout_s(i - 1);
      end loop;
    end if;
   end process;
end A_rn;