Theo Verelst Processor Core page

About 20 years ago, I had a box with TTL parts, and I made a 4 bit (slice) breadboarded processor core with addition, logic operations, storage, and (conditional) jumps.

Now, I want to use a modern design environment to do basically the same, starting in some senses simpler, but with an 8 bit bus. It is first of all a test for serious designs (I already hit all the demo limations, funding is very needed here), and because I want to prepare a design for doing waveguide processing, and to implement that either on a PCB with random logic, on an FPGA, or other carriers (which is automatically possible using vrious design packages).

A Processor Core

I've recently included a larger file, the project archive , which contains all the data to do simulations. Mind that it is a version where I cranked up the clock to 10MHz, and the circuit can't (yet) handle that, so you'l need to tweak the two stimuli (the reset and the clock) to 1 tenth of their current settings to get a certified working circuit.

Here is a version (ca 45 Kbyte Microsim archive) that does work at 5 MHz (including a clock delay gate..) in Microsim archive form. Load it in the design manager, expand it, double click on the schematics symbol to open 'pcore.sch' in the schematic editor, press 'simulate' and the results will be shown on the screen. The critical path is the path through the instruction cycle counter, decoder, instruction decoder, and random logic to the load input of the program counter, which adds up to some 75nS, thus limiting the clock rate. It should be easy to replace this by a two level deep logic block, to get into the more serious clock frequency ranges.
I also made a printed circuit board design for part of this diagram, because there are too many parts in there for the demo version to handle, which works fine when leaving the memory out, because there is no pindef for it (with its seperated in and out bus it seems pretty uncommon anyway). The adders and buffers I could put on a printed circuit board in about 15 minutes, assuming the results can be read easily to actually produce the board.

The Microsim package can be freely downloaded in the demo version after filling in some forms from here .

An image of the version 1.0 in buildup but tested stage, note this design has arisen in about a work day's time, so its hardly thoroughly tested:

The following is the program I put in the memory for a test run:

* My first program...
*
* Test program for the 'pcore' processr core, 
* testing, NOP, load, and conditional jump instructions.
* It is inteded to generate samples, when its datapath 
* is slightly extended, but it acts as a fairly ordinary 
* microprocessor as well.
*
* I might extend the microprogram with more instructions, since
* it would be easy to add some more storage and logical 
* functions, but I'm already close to the maximum number 
* of nodes and logic transitions in my demo version of the 
* microsim spice simulator, so I'm not sure that's 
* immedeately possible.
*
* At any rate, the instruction and data path spectrum is
* roughly traversed (except for an extended and 3 state
* address and data bus, see above remark).
*
* The program in assembler type format (done by hand,
* at this time):
*
*Label
*|    Address
*     | Opcode/dat
*       |  Mnemonic
*          |   operands
*              |            comments
*--------------------------------------------------------
      0 14 Jmp 4          ; Jump to loop-1
      1 00 Nop            ; (skipped, test purposes)
      2 00 Nop
      3 00 Nop
      4 00 Nop
loop  5 30 Ld  reg0, F8   ; Load the first adder-register
                          ; (alternatively, 18h is loaded)
      6 F8 
      7 31 Ld  reg1, 19   ; idem for second
      8 19 
      9 25 Jmp nc, loop   ; Jump back to loop on no carry
 
      A 00                ; random memory contents ...
      B 02 
      C 00
*     ...
*---------------------------------------------------------
The memory is filled in advance, by adding the above data 
to the memory initialization definition in the Spice code 
(I hacked it in the library, I'll bet there are official ways 
of doing this neatly for a 8K*8 memory type instance.)
If you want to change the program yourself, you'll need 
to edit the lib/BREAKOUT.LIB file, and search for the following 
section:

.SUBCKT RAM8Kx8Break RE WE
+                    A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
+                    W7 W6 W5 W4 W3W W2 W1 W0
+                    R7 R6 R5 R4 R3 R2 R1 R0
+                    OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+                    PARAMS: MNTYMXDLY=0 IO_LEVEL=0


U1 RAM(13,8) DPWR DGND RE WE 
+            A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
+            W7 W6 W5 W4 W3W W2 W1 W0
+            R7 R6 R5 R4 R3 R2 R1 R0
+            RAM8Kx8_TIMING IO_STD
+            MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
* The next is added (F8 is changed to 18 for no carry):
+            DATA=X$ 14 00 00 00 00 30 F8 31 19 25 00     02 00 10 FF 00 FE 01 80 80 00 01 02 03 04 05 33 34 35$
*+            FILE=ramini.hex

The simulation results for taking the added values to be 0x18 and 0x19 (Hex), leading to a conditional jump causing a (infinite) loop are:

and the simulation results for computing the sum of F8H and 19H, leading to a carry or overflow signal causing no subsequent jump, are,

Simulating on a pentium (100MHz) is quite fast, simce there are no analog parts, about 10 seconds gets the next results on screen. Experiment with given circuit diagram (if you dare), using this stimulus file .