Testing of sequential circuits requires that test patterns be applied in a specific sequence. On-chip test pattern generators often suffer from the problem that it requires incorporation of idle cycles between the test patterns. In this paper we present a scheme that can generate any given sequence of test patterns using cellular automata (CA) and some associated circuitry without any inserted cycles. This also results in up to 95% reduction in memory management over the direct storage of patterns. Moreover, regular, modular, and cascadable structure of CA with local interconnections make the scheme ideally suited for VLSI implementation.

With time-to-market becoming a key factor in the success of any IC product, lot of stress is being put on integrating test development with device simulation so that the test solutions are ready before the actual silicon comes out.

Texas Instruments has worked with EDA (Analogy and Cadence) and ATE (Teradyne) companies to develop a Mixed Signal Test Simulation Flow which facilitates circuit simulation of the target ATE, Teradyne's A5XX mixed signal tester, and the device under test (DUT). The exchange of events between ATE and design models take place in the common Saber-Verilog mixed signal simulation environment wherein simulations are controlled from the test program which gets executed on Image, Teradyne's tester control software. Simulation results are available for analysis in both ATE debug tools and design simulation tools. The analog partitions of both ATE and DUT use Saber as the simulator, which uses MAST for modeling analog components, whereas digital partitions are simulated using Verilog-XL.

Image Exchange module, developed by Teradyne, specifically for exchanging events for test simulations, generates time stamped event record of the tester hardware bus as the program executes and these are passed through Verilog to be converted into design simulator stimulus. Design simulation results are applied as tester hardware bus events to Image, which further applies them to the test program variables and the debug windows.

This flow was used to develop the test program for a 12-bit, 200KSPS ADC. All the digital patterns where debugged using this flow. This helped in reducing the test program debug time on tester from eight weeks to six weeks, a saving of about 25 percent.

This flow was used to develop the test program for a 12-bit, 200KSPS ADC. All the digital patterns where debugged using this flow. This helped in reducing the test program debug time on tester from eight weeks to six weeks, a saving of about 25 percent.

In our design, for an n-input CUT, TPG generates all n.2ⁿ SIC pairs by a sequence of 2n.2ⁿ vectors. SA observes the transitions at each odd pair. More specifically, SA checks whether there is any transition of 1 to 1 or 0 to 0 in the output response while applying the 1^st and 2^nd inputs, 3^rd and 4^th inputs, 5^th and 6^th inputs, and so on. Notice that SA does not observe the transitions in the output corresponding to 2^nd to 3^rd input, 4^th to 5^th inputs, 6^th to 7^th inputs, and so on. To implement this, SA also keeps track of the inputs and at every even pulse it counts the transitions. In the design of TPG, a 2n-bit circular shift register (SR) is used. Outputs of odd stages of (SR) are connected to n XOR gates to change one bit of a vector X_i produced by a n-bit binary counter (BC). The test pattern generator (TPG) generates a sequence X_i¹, X_i, X_i², X_i, X_i³, X_i,……., X_iⁿ, X_i, for every possible input X_i, where X_i^j differs from X_i only in j-th bit.

The scheme detects multiple stuck-open and path delay faults in two-level circuits by counting the number of transitions at the output of the CUT. TPG generates a sequence of length 2n.2ⁿ for an n-input CUT. Transitions are counted corresponding to inputs at odd pairs.

In traditional IC design, every circuit is designed more or less from scratch and Reuse is limited to standard-cell libraries, containing basic logic gates. This design style is being re-placed by one in which an IC consists of multiple, large, Reusable modules and also dedicated modules. These large, Reusable modules are called Cores; examples are CPUs and memories. Cores might come as hard(layout), firm(netlist), or soft(RTL).

Core-based design divides the design community into two groups: Core Providers and Core Users. Because short time-to-market is the driving force behind Core-based design, Cores often come with pre-computed tests for manufacturing defects. These tests can be based on various test methodologies, such as function test, scan test, or built-in self test. The Core user has to take care that suitable access paths from IC pins to embedded Core and vice versa exist, such that the pre-computed test patterns can be transported to and from the Core.

The use of embedded cores in the rapid construction of systems on silicon has opened up new challenges in VLSI testing. An important one among them is the need to meet the high fault coverage goals in an embedded context. While conventional design for test techniques have addressed this problem for individual chip designs, in an embedded context, the fault coverage is influenced not only by the cores themselves, but also by the logic surrounding them, memories, and test interfaces.

This presentation discusses major techniques for enhancing the fault coverage of core based systems. It reviews the design components of these systems, how they impact the coverage, and techniques to improve the latter. Various testability enhancement techniques, based on the design methodology, preferred system configuration, fault grading of verification test cases, efficient generation of such tests for targetted faults and fault models, BIST, and fault analysis of undetected faults, are described. It is shown how each of these techniques and their combinations plays an important role in test of embedded core based systems, and how restrictive they are when considered in isolation.

These techniques have been evaluated on Texas Instruments’ new DSP core, TMS320C27xx, and devices using this core. Through a careful selection of these techniques, the fault coverage of the various modules built into devices using this core have been successfully raised, in an embedded context. These improvements have, in turn, also influenced the design of the core and the system themselves.

The memory section of chips with embedded memory is more prone to defects in the production process than the other parts. Therefore, during design phase, special attention has to be given to the integration of memory in order to enable effective testing of whole chip. In designing testable memories and logic, the first step is to define the global test strategy. The four basic test methodologies available for memory are

Before choosing the test methodology, certain aspects have to be considered like Fault coverage, test time, Area usage, Diagnostics, Protection, etc.. The importance of these items may vary greatly from one chip to another.

Out of above four test methodologies, Scan Test is the way to test random logic. The principle of Scan Test can also be used for geting access to the embeded memories in the circuit. Built-in Self Test is, in general, most effective for larger memories. The execution time is short compared to scan test approaches. The embedded memories can be accessed through multiplexers also, The speed of testing is high compared to scan test. One drawback of this test is that many pins are used as test pins. In the situation where all the memory signals are connected to chip pins the memory is accessilbe and testable from the external world. In such cases it is easy to test the memory functionally. In this paper we will discuss more about Scan test.

Most systems on chip today contain both digital and analog components. Testing of analog circuits is therefore gaining considerable amount of importance. The tutorial will discuss techniques for testing analog circuits.

This tutorial discusses a number of approaches to the verification of RTL designs generated by high-level synthesis systems:

With the growing complexity of systems-on-chip (SOC), testing them has emerged as a daunting problem. In this paper, we shall consider the problem of testing a system-on-chip without violating a user-specified power constraint. Power dissipation is an issue in testing of SOC due to several reasons. Since test vectors are generally applied in an uncorrelated manner, the power dissipation of an embedded core can be several times the power dissipation during normal mode of operation. When there are many embedded cores on the SOC, if their test sessions are not appropriately scheduled, the power dissipation can exceed the power rating of the chip. We provide a greedy algorithm for scheduling test sessions. The objective of our algorithm will be to minimize the test application time. We present results on two example designs.

This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that first 2k vectors cover all adjacent k-bit spaces exhaustively. It requires substantially lesser hardware than the existing methods, and utilizes the regular, modular, and cascadable structure of local neighborhood cellular automata (CA) that suits ideally for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15-50%. Moreover, testing methodology and hardware requirement have been established analytically, rather than by simple simulation and logic minimization.

There is a tremendous growth in the complexity of VLSI systems being designed today. To be cost effective and remain in competition, there is always a need to reduce duration of design cycle. Decision for design process improvement have been, traditionally based upon historical data and designers’ perceptions of critical sections of design process-flows.

Since design processes also continue to increase in complexity, it becomes mandatory to base process improvement decisions on quantitative analysis. We propose an analytical technique for modeling of concurrent design processes. We call it Extended Signal Flow Graph ( ESFG ) technique.

It has some extended features over existing Signal Flow Graph ( SFG ) technique. Our approach is capable to capture concurrent behavior of design process flows and unlike SFG technique, is able to provide total completion time for a design process. SFG technique when applied to model a concurrent process, can only provide with total efforts in design process, instead of process completion time. We illustrate our approach by implementing it for a abstract design flow for wireless mobile transceiver design.

I. Timing Closure for SoC designs

• SoC requirements with an example. Concepts: Static v/s Dynamic timing
• Chip-designers perspective (Block, Full-chip)
• EDA vendors' perspective (tools, flows)
• Challenges ahead (Technology, Ease-of-Use, Productivity)
• Key takeaways for SoC designers

II. SoC requirements for timing closure

• Four primary design styles {ASICs, ASIC-SoC, Custom-SoC, Full-Custom}
• Typical SoC design (IP, synth, custom, clk.tree, pwr/IOpads)
• Design flow (P&R, RTL->netlist, Layout/extract, TC, SignOff)
• "Time to Market" => Reduce Iterations with user-control
• Example: MPU-core in a hi-end chip (incl. memory)
• Timing checks: SetUp/Hold definitions, flat v/s models tradeoffs

III. Chip-perspective

1. Full-Chip (P&R, budgets, routing, clk-tree, parasitics)
2. Block (EVR, sub-partitions, gate/trans, static/dynamic, BVR)
3. Full/Block iterations, top-five methods of fixing violations :

• Block/Static-gate to Custom(incl.Domino)
• Block/Skew-gates to enable transistions (noise-margins!)
• Re-partition or re-synth blocks w/ new constraints
• Latch transparencies; hold-time checks
• Full/ repeaters (or stronger buffers)

D. Analysis, Extraction, Optimization, Verification, Modeling

IV. EDA perspective

• BFS v/s Depth First Search approach, tradeoffs
• Path-based algorhithms @ block-level; accurate RC-simulations
• Batch v/s Interactive, Data-visualization and EzU
• RC/CC Extractions; capacity/runtime/accuracy and "right partitions"
• Models: Data-size v/s visibility, re-use, sender/receive environments
• Timing budgets (accuracy for CTX is vital)

V. Challenges ahead

• Process-Technologies: Accuracy = {model+simulation}; DSA approach
• SOI/Copper, Mem+Logic implications on SoC
• Accuracy, Runtime v/s TTM for larger, more complex blocks
• IP-reuse (soft/hard) Cost v/s Utility (process dependency)
• Multiple Voltages, Complex clock-trees, multiple (asynch?) clocks
• { Signal Integrity + STA }
• Expertise from EDA/R&D to Designers; new business model needed ?

VI. KEY takeaways for SoC designers

1. Marry your methodology into the EDA flows based on your tradeoffs for accuracy/runtime/capacity

2. Logic & Ckt. partitioning to stay flexible

3. More Analog, more custom content. Analog-IP is a myth !

4. STA is the way to go, with Dynamic-on-Demand

5. "Closure" not "Analysis" is the key; less scripts is better.

6. New business models could mean iSolutions; smaller blocks is better

7. "Work at gate-levels, performance at transistor-levels"; models for IP-reuse is gaining in importance

8. Do not throw your "EE/circuit-design" books away.. yet !

9. No "estimates" in the new world; accuracy for CTX and CSO is key !

10. Review your RTL with a circuit-team before you encode your block.

A low voltage embedded single port memory generator implemented in a 6 metals, 0.18um standard CMOS process is described. The typical (8kx16) cut is achieving 300Mhz maximum frequency, with a 3.3ns access time at 1.3V and 25ºC and a typical power of 180uW/Mhz at 1.3V. Special care has been taken to reduce the standby current. The hierarchical wordline architecture, and a differential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder.

Memory is an important component of computers along with central processing unit and input-output devices. As the number of memory chips is significant in the total number of chips in a computer, to ensure that the overall system functions properly, it is necessary to make sure that each chip in the memory subsystem is functionally correct. Thus testing of memory chips has become compulsory.

A memory chip in general consists of three blocks: Memory cell array, Address decoder, and Read-Write logic. In an embedded memory chip all these three blocks will be integrated onto a single chip. In any CMOS circuit power dissipation depends on the switching activity in the circuit, load capacitance and voltage swing at the output node. In this work, power dissipation during testing of a memory chip has been estimated for four traditional test methods and for pseudo random testing.In addition to the general architecture, devided word-line architecture is also considered as a low power alternative. For each of the test methods and architectures, expressions are derived for transition density, which is a measure of switching activity and load capacitances associated with each block.These expressions are general w.r.t memory size. Then average power dissipation is estimated for each block which are summed up to get the overall chip power.

In testing it is desired to complete the testing of all chips with in minimum possible time. With this objective the most efficient solution is to conduct tests for all chips symultaneously. But, the power dissipation of a test session should not exceed the maximum power rating of the system under test. So, an optimum solution is to be extracted which can minimize the overall test time while satisfying the power constraints. A scheduling algorithm is developed which gives an optimum solution in all possible cases. This algorithm also considers the resource conflicts while scheduling tests. In case of built-in Self-test, the power dissipation in BIST hardware can also be considered while scheduling which gives an accurate solution.

The paper presents a methodology for achieving the desired area-delay-power tradeoffs for the weighted-sum based DSP kernels, the building blocks of embedded, real-time DSP based SoCs. We propose a framework that encapsulates various algorithmic and architectural transformations and enables systematic exploration of the area-delay-power solution space of DSP algorithms for a given implementation style. The framework is based on a classification of the transformations into seven categories which exploit the unique properties of DSP algorithms and the implementation styles.

Here are the seven categories of transformations:

* Implementing data movement by moving the pointer to the data

* Data Flow Graph Restructuring Transformations

* Data Coding

* Transformations that Exploit Redundancy in the Computation

* DFG Transformations based on Mathematical Properties

* Exploiting Relationship between the Real Value Domain and the Binary Domain

* Transformations that Exploit Available Degrees of Freedom

We discuss the specific transformations for each of these categories in the context of five implementation styles and highlight how the desired area-delay-power tradeoff can be accomplished.

Here are the five implementation styles:

* Programmable processor based implementation:

* Implementation using hardware multiplier(s) and adder(s)

* Distributed Arithmetic based Implementation

* Multiplier-less Implementation

* Residue Number System based implementation

As battery operated environments become increasingly programmable, the power dissipation aspects of the embedded computing engines in these devices are a growing concern. A number of such devices employ programmable DSP processors due to the nature of computation involved in their function. Low power design techniques have been an active area of research for a number of years now and methods to reduce power have been proposed at all levels - from system to device. Of these a number of techniques work at the micro-architectural level to reduce power dissipation and even the energy requirements of typical computational loads. Reduction in the energy consumption has a direct impact of extending battery life and enables the use of smaller and lighter batteries that reduce the overall system cost.

This paper is a survey/review of the low power design techniques that focus on the micro-architectural level, in the context of DSP processors. The power dissipation in a microprocessor is concentrated in the memory subsystem, the arithmetic processing datapath, the instruction fetch logic, the register file and the instruction decode. Opportunities and techniques for power reduction in each of these units are reviewed and the tradeoffs involved are discussed. Some of these techniques are essentially software techniques with some hardware support so one may still consider them to be micro-architectural level optimizations.

The techniques covered for each major subsystem in a DSP are :

• memories, busses and fetch units - Data arrangement in memories (blocking, coefficient reordering, address space mapping, memory banks and load time optimizations), coding of data for reduced bus activity (gray codes, T0 coding, bus invert coding), pipeline gating, effects of cache organization.
• datapath - power management techniques (guarded evaluation, precomputation, operand swapping), residue arithmetic implementations, specialized functional units, reduced precision arithmetic, impact of subword arithmetic, reconfigurable datapaths.
• register files - clock gating, register reassignment, partitioned register files.
• instruction decode - opcode assignment, some instruction scheduling effects, loop buffers.
• system parameters - dynamic voltage scaling.

System-Level considerations are as important as --- and sometimes more important than --- circuit-level techniques for power optimisation. This paper begins by presenting various aspects of system-level optimisation techniques including algorithm selection and applications technology selection. Then it looks at various techniques for dynamic power management especially in the context of DSP and communication domains. Finally, a glimpse is presented on how asynchronous circuits can provide us a lead for the future.

Digital waveform generators (DWAGs) are integral part of the modern communication system, such as TV [Xia], video monitors, mobile networks, and other applications where proper synchronization is necessary between transmitting and receiving end. While conventional goals such as minimal area and maximal performance continue to hold, additional constraints such as testing has to be considered. Generally it is seen that area constraint also cures the other two problems to a large extent. In this paper we present some design tips resulting in an easy testable and area efficient DWAGs, which is very difficult with the present day’s limited knowledge of circuit synthesizers. In a case study we show that it’s not impossible to get 103 to 105 time improvement [Hasan] in the area as compared to conventional methods, provided the desired waveforms are repeatable in nature.

A general architecture of Motherboard Clock generator is presented. Major subblocks like PLL, divider and output paths are described. Spread Spectrum technique to reduce EMI is discussed. Current Steered Differential output is presented to show how it reduces jitter.

We study the problem of resizing gates so as to reduce overall power consumption while satisfying a circuit’s timing constraints. Polynomial time algorithms for series-parallel and tree circuits are obtained. Gate resizing with multigate modules is shown to be NP-hard.

A well known approach to floorplanning is based on rectangular dualization[L90]. This makes use of triangulated adjacency graphs with certain characteristics. It is well known that if the input adjacency graph to the floorplanning phase contains a cycle of length three that is not a face (complex triangle), transformation of the graph into a rectangular floorplan is impossible. Thus complex triangles (CT) have to be eliminated before the floorplanning phase. Complex triangle elimination (CTE) in weighted adjacency graphs has been shown to be NP-complete in [SY93]. [SY93] also proposes a method for CTE problem for graphs without any nested complex triangle. A well known approach to floorplanning is based on rectangular dualization[L90]. This makes use of triangulated adjacency graphs with certain characteristics. It is well known that if the input adjacency graph to the floorplanning phase contains a cycle of length three that is not a face ( complex triangle ), transformation of the graph into a rectangular florrplan is impossible. Thus complex triangles (CT) have to be eliminated before the floorplanning phase. Complex traingle elimination (CTE) in weighted adjacency graphs has beeen shown to be NP-complete in [SY93]. [SY93] also proposes a method for CTE problem for graphs without any nested complex triangle.

In our work, we consider the more general CTE problem for adjacency graphs with multiple levels of nesting of CTs. We prove the problem to be NP-hard by showing its polynomial-time reducibility from a well-known NP-complete [GJ78] problem. We use edge-covering technique for solving the problem.

The input to our problem is an unweighted adjacency graph G with complex traingles, and our goal is to find the minimum number of edges in G, removal of which will eliminate all the CTs in G. The input adjacency graph is mapped into a dual graph G’, each vertex of which corresponds to a CT, and two vertices have CTs have a common edge. We next employ a best-first search strategy which attempts to find a minimum set of cliques in G’ such that all vertices of G’ are covered. In each stage, a lower bound lb on the additional numberof edges in G for CT elimination is estimated. To compute lb, the graph G is preprocessed, by coalescing all CTs within some other CT into a single vertex, such that the reduced graph Gr has no nested CT. At a stage, once a clique in Gr is chosen, its corresponding edge in G is eliminated, and G is modified.

The proposed algorithm has currently been implemented on some randomly generated triangulated graphs using C/C++ on Pentium PC. Our work will have interesting applications to generate triangulated graphs which have rectangular floorplan realizations. An extension of this work would be rectangular graphs with nested complex 4-cycles, in which pseudo-vertices may have to be added to ensure slicibility [YS95].

Two-dimensional placement is an important problem for FPGAs. Current FPGA capacity allows one million gate equivalent designs. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. We propose to use the tabu search optimization technique for the physical placement step of the circuit mapping process. Our goal is to reduce the execution time of the placement step while providing high quality placement solutions. In this paper we present a study of tabu search applied to the physical placement problem.

First we describe the tabu search optimization technique. Then we outline the development of a tabu search based technique for minimizing the total wire length and minimizing the length of critical path edges for placed circuits on FPGAs. We demonstrate our methodology with several bench mark circuits available from MCNC, UCLA, and other universities. Our tabu search technique has shown dramatic improvement in placement time relative to commercially available CAE tools (20$\times$), and it results in placements of quality similar to that of the commercial tools.

Dinesh Bhatia received a Bachelor’s in Electrical Engineering from Regional Engineering College, Suratkal, India in 1985 followed by a MS and Ph.D. in Computer Science from University of Texas at Dallas in 1987 and 1990 respectively. His doctoral work was supported by ACM SIGDA scholarships.

He joined the Computer Science and Engineering Department at the Southern Methodist University

.

In a semiconductor industry it is important to win a customer by providing a product with the lowest cost and best performance. Lower the die size lesser the cost of the chip. Hence die size reduction is one of the major contributors for earning higher net revenue per wafer. To achieve die size reduction without sacrificing the performance there is a need for an efficient layout. An auto layout tool generates a module layout using library cells; the area efficiency reported by this solely depends on library cell area provided. If the library cell is not drawn with high efficiency the report may not be genuine. Hence there is a need for gauging the layout efficiency with higher accuracy for any given layout. There has to be a tradeoff between the performance of the chip and the die size when it is an analog layout. For digital layout as the logic is relatively high, the available area has to be utilized to a very high factor.

PHYSICAL LAYOUT EFFICIENCY CHECKER methodology speaks about reporting an overall efficiency of the drawn layout. Generally as the power routing is planned on the top most METAL layer, using this methodology the efficiency of power distribution can also be reported. More importantly a feedback mechanism is provided for under utilized area considering design and process constraints. Hence it provides a genuine solution to report the layout efficiency and reduce the die area, thus improving net revenue per wafer.

In this paper, we examine the state assignment problem as that of embedding a given finite state machine in the Kronecker product of two smaller machines. To construct the smaller machines, the states of the original machine are partitioned in two different ways such that the resulting partitions have their ‘meet’ as the singleton partition. We propose a cost function for this ‘decomposition’ which would reflect the cost of realization of the machine through the Kronecker product. The cost function is justified theoretically, using a model of multi-level implementation as well as empirically, on a particular benchmark. We describe a simple algorithm to minimize this cost function. We obtain empirical results by running the algorithm on a set of 16 MCNC benchmarks and using one-hot encoding for implementation of decomposed machines. For multilevel implementation, the results show an average reduction of 8.52% in area and 81.87% in delay when compared with implementations obtained using JEDI, and an average red uction of 4.40% in area and 104.96% in delay when compared with implementations obtained using NOVA. This scheme has the potential to serve as an alternative to conventional state assignment tools since we observe that it works well for larger finite state machines. It also appears equally promising for reduction of power consumed using gated clock, since the partitions can be chosen such that the corresponding machines have maximum number of self-edges.

ElectroStatic Discharge (ESD) is the transient discharge of static

charge from one body to another. ESD is caused when two bodies, at

least one of them being charged, come in contact. In the

semiconductor industry, ESD is a serious reliability issue because of

the high voltages and current densities which appear during an ESD

strike. These cause irreparable damage to ICs like gate oxide

breakdown and contact spiking. The ICs become more and more

susceptible to ESD as their dimensions shrink and their complexities

increase. Hence it becomes absolutely essential to ensure that an IC

is safe from ESD throughout its lifetime. Various protection

strategies have been proposed from time to time. These include both

on-chip and off-chip protection. This paper focuses on the on-chip

strategies and proposes a more effective way of verifying them. The

on-chip ESD protection strategy is simple, Clamp the voltage below the

gate breakdown voltage as well as provide a low resistance path during

ESD strike so that the ESD current does not affect the output buffers.

As ICs become more and more complex, just having a protection device

at every pin is not enough because of sneak paths present in the core

of the chip. To take care of all these issues a set of ESD design and

layout guidelines exist which have to be followed strictly to ensure

ESD robustness. Hence it becomes extremely critical to verify that

the layout adheres to these ESD guideline before sending the layout

Layout is the physical representation of an Integrated Circuit. Parasitic are unintentional devices that are present in the layout. These parasitic are formed due to the interconnections between the circuit components. The Parasitic will alter the circuit performance by adding unintentional resistance and capacitance. Therefore, for any critical analog designs, it becomes very essential to extract these parasitic devices from the layout and analyze what will be the actual circuit performance. The extracted devices can be modeled as lumped resistance and capacitance and can be added with the schematic for simulation. This flow is called as Back-Annotation.

Lot of EDA tools are available today to extract parasitic from the layout. Each follows different algorithms to extract. This paper won’t talk about the above said topic. This paper is concentrated on integration of all different steps which are involved in parasitic extraction in to one and also about the provision of an intermediate step of giving the parasitic information in the layout.The intend is to help layout designer to do their layout efficiently with less parasitic and also to reduce the cycle time by providing a complete automated flow for Back-Annotation.

The proposed methodology here is an effective way of executing the Back -Annotation flow. This methodology integrates all the steps involved in Back-Annotation,which helps in reducing the cycle time.Also it gives a visual representation of the Parasitic devices in the layout.This helps the layout designer to get an idea of how to reduce the parasitic elements in the Layout.

We have considered the problem of scheduling the operations of data flow in a reconfigurable computing environment. In the recent years, FPGAs have become highly popular as a medium to rapidly prototype complex systems. As the FPGA technology improves i terms of speeds and te number of gates/chip, FPGAs are being used in system construction and not just for prototyping. Some innovations such dynamic and partial reconfiguration of FPGAs has opened new doors to high performance computing using dynamically

reconfigurable FPGAs which uses a limited number of FPGA chips to run a large computation within a time limit. In this paper, our intention is to describe the problem of operation scheduling in such a dynamically reconfigurable environment. We shall first classify the various reconfigurable computing environments and develop an optimizing criterion for problem of operation scheduling. A heuristic algorithm for operation scheduling is then described and its performance is studied on several examples.