About the speakers

Juan C. Rey, Mentor Graphics Corporation

Juan C. Rey is the Senior Engineering Director for the Design to Silicon Division at Mentor Graphics Corporation; his group is responsible for the architecture, design and development of the Calibre line of products used for integrated circuits physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing.

Juan has 25 years of software development experience ranging from research activities at Stanford University (EE department), to development and management (at Technology Modeling Associates, Cadence and Mentor Graphics) of process and device modeling software. His most recent 15 years have been in Electronics Design Automation and semiconductor processing modeling.

Srinivas Mandavilli, Mentor Graphics India

Dr. Srinivas Mandavilli heads the Hyderabad R&D center of Mentor Graphics India. Mentor Graphics Hyderabad has been in operation for around 10 years and has an employee strength of around 225.

Prior to joining Mentor Graphics, Srini has served in various engineering and management roles at Ionic Microsystems, Motorola, and Hitachi Semiconductor America.. He holds a Ph.D in Computer Science from the Indian Institute of Science, Bangalore, and a B.Tech in Electronics from Indian Institute of Technology, Madras. For his Ph.D thesis in Genetic Algorithms, Srini received the best Thesis award at IISc in 1993, and had over 10 international publications.

Kazuya Masu, Tokyo Institute of Technology

Kazuya Masu received the B.E., M.E. and Ph.D. degrees in Electronics Engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1977, 1979 and 1982, respectively. He was with the Research Institute of Electrical Communication, Tohoku University, Sendai, Japan since 1982. In 2000, he moved to Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama, Japan and he is currently a professor in Integrated Research Institute, Tokyo Institute of Technology. He was a visiting Professor in Georgia Institute of Technology in 2002 and 2005. His current interests are signal integrity and GHz signal propagation in multilevel interconnect of Si ULSI, reconfigurable RF circuit technology, LSI performance evaluation and prediction based on statistical approach, and BEOL process technology.

He received IEICE Electronics Society Award in 2005. The paper presented at A-SSCC2006 (IEEE Asian Solid-State Circuit Conference) has awarded as Student Design Contest Outstanding Design Award.  He served technical program committee member of international conferences of IEDM (IEEE International Electron Device Meeting), SSDM (International Conference of Solid State Devices and Materials), ADMETA (Advanced Metallization Conference: Japan Session), etc.  He is a member of the IEEE, the Japan Society of Applied Physics (JSAP), the Institute of Electronics, Information and Communication Engineers (IEICE), the Institute of Electrical Engineers of Japan (IEEJ), Japan Institute of Electronics Packaging (JIEP), and the Electrochemical Society (ECS).

Ersed Ackasu, OEA International, Inc.

Osman Ersed Akcasu was born in November 3rd 1955 in Istanbul, Turkey. Graduated from Technical University of Istanbul in 1977 with BSEE in Electrical Engineering. In 1980 he received his Ph.D. from University of Bradford, England in Solid State Electronics. His Ph.D. dissertation was “Two Dimensional Mathematical Modeling of Bipolar Transistors”. He worked for Harris Semiconductor, Fairchild Semiconductor, Cray Research and Brooktree Corporation, all in the areas of Process and Device Physics and Architecture. Since 1986 his interest was in interconnect related mathematical modeling. In 1988 he founded OEA International, Inc., which is primarily focused on interconnect modeling. He has more than 30 technical articles as first author and several patents.

Noel Menezes, Intel Corporation

Noel Menezes manages Intel's Strategic CAD Labs, which is part of the Design and Technology Solutions division.  In the past, he worked on the first automated interconnect design solution applied to Intel's Pentium 4 family of microprocessors.  His graduate work on clock tree synthesis and the C-effective delay model for static timing analysis has been applied in the CAD suites of several EDA vendors and VLSI design companies. His current research interests are on techniques to analyze and mitigate the impact of variations in design and advanced cell delay models. Noel holds a B.E. degree from the Maharaja Sayajirao University, Vadodara, and M.S. and Ph.D. degrees from the University of Texas at Austin.

T.W. Williams, Sysnopsys

Dr. Thomas W. Williams is a Synopsys Fellow at Synopsys in Boulder, Colorado, U.S.A.  Formerly, he was with IBM Microelectronics Division and manager of the VLSI Design for Testability group. He received a B.S.E.E. from Clarkson University, an M.A. in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University. He has received numerous best paper awards from the IEEE and ACM, is the founder or co-founder of a number of workshops and conferences dealing with testing, and was twice a Distinguished Visitor lecturer for the IEEE Computer Society.

Dr. Williams has previously served on the Computer Society Board of Governors and the IEEE Board of Directors, and was the Society’s 2000 Treasurer. He is a member of the Eta Kappa Nu, Tau Beta Pi, IEEE, ACM, Sigma Xi, and Phi Kappa Phi. He is an Adjunct Professor at the University of Calgary, Calgary, Alberta, Canada; and in 1985 and 1997, he was a Guest Professor and Robert Bosch Fellow at the Universitaet of Hannover, Hannover, Germany. He was recently named a member of the Chinese Academy of Science. Dr. Williams was named an IEEE Fellow in 1988 and received the Computer Society’s W. Wallace McDowell Award for outstanding contributions to the computer art in 1989. In 2007 Dr. Williams received the European Design and Automation Association Lifetime Achievement Award for “outstanding contributions to the state of the art in electronic design, automation, and testing of electronic systems.”

Sachin Sapatnekar, University of Minnesota

Sachin Sapatnekar received the B. Tech. degree from the Indian Institute of Technology, Bombay in 1987, the M. S. degree from Syracuse University in 1989, and the Ph. D. degree from the University of Illinois at Urbana-Champaign in 1992. He has worked at Texas Instruments during the summer of 1990, and at Intel Corporation during the summer of 1997.

He was an Assistant Professor in the Department of Electrical and Computer Engineering at Iowa State University from 1992 to 1997. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits, and are primarily centered around physical design, timing and simulation issues, and optimization algorithms. He has authored/coauthored/co-edited five books and has served on the editorial boards of the IEEE Transactions on VLSI Systems (current) and the IEEE Transactions on CAD (currently as deputy editor-in-chief) and the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (in the past), has served on the Technical Program Committee for various conferences, including as technical program co-chair for DAC 2006 and 2007. He has been a Distinguished Visitor for the IEEE Computer Society and a Distinguished Lecturer for the IEEE Circuits and Systems Society, and is a recipient of the NSF Career Award, the SRC Technical Excellence Award, and best paper awards at the DAC'97, ICCD'98, DAC'01 and DAC'03 conferences. He is a Fellow of the IEEE.

Steffen Rochel, Blaze DFM Inc.,

Dr. Steffen Rochel is the vice president of engineering, Blaze DFM. Dr. Rochel has over 15 years of development and management experience with successful startups and established EDA companies such as Anacad, Mentor Graphics, Simplex Solutions and Cadence. Prior to Blaze, Rochel managed the research and development teams for a number of product lines and technologies at Cadence. He joined Cadence by way of the acquisition of Simplex Solutions where he led the development of the VoltageStorm product line. He has a Ph.D. and Diploma in Electrical Engineering from the Technical University Ilmenau in Germany and has co-authored and presented more than 25 conference papers, journal articles and seminars.

Nishath Verghese, Cadence Design Systems

Nishath Verghese received his BE in Electrical Engineering from BITS, Pilani in 1990, MS and Ph.D in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh in 1995. He was a principal at EDA startups Apres Technologies and CadMOS Design Technolology, which was acquired by Cadence Design Systems in April 2001.

From 2001-2004 he was director of timing and signal integrity products in the Digital IC division of Cadence. Subsequently, he was VP, R&D for design products at Clear Shape Technologies, a startup, specializing in model-based DFM analysis software tools. Since Clear Shape’s acquisition by Cadence in August 2007, he is serving as group director of electrical DFM and extraction products at Cadence.

Atul Sharan, Cadence Design Systems

Atul Sharan is a 20+ year veteran of the hi-tech industry with experience as an engineer, manager, entrepreneur, senior executive, angel and venture investor. Most recently he was co-founder, President and CEO of Clear Shape Technologies, Inc., which was acquired by Cadence. Prior to Clear Shape, from 1998 to 2003, Mr. Sharan was Senior Vice President, Sales and Marketing for Numerical Technologies, Inc. During his tenure at Numerical, the company grew from pre-revenue stage to a highly successful IPO in April 2000 and was eventually acquired by Synopsys in 2003 where he served as Vice President. Subsequent to that he was resident at Mohr-Davidow Ventures. From 1997 to 1998 Mr. Sharan was in charge of key partnerships and business development at Ambit Design Systems - the company was acquired by Cadence Design Systems in 1998.

From 1991 to 1997 Mr. Sharan held senior management positions at Compass Design Automation. While at Compass as General-Manager, India Operations, Mr. Sharan helped establish a software development center in India. From 1984 to 1991, Mr. Sharan worked in semiconductor manufacturing operations at VLSI Technologies and Integrated Device Technology. At IDT Mr. Sharan helped initiate the company's first overseas Test and Assembly plant in Penang, Malaysia. Mr. Sharan has an MBA from University of California, Berkeley, an MS in Engineering from Texas and a B. Tech Degree in Engineering from IIT, India. He is a charter member of TIE.

Nagaraj N.S., Texas Instruments Inc., Dallas

Nagaraj NS is the Director of Interconnect Modeling, Design and Performance Closure at Texas Instruments Inc., Dallas, TX. Over the past 17 years, the design methods and solutions developed by him for signal integrity, interconnect modeling, RC extraction, IR-Drop, reliability, variability and DFM in advanced CMOS technologies have been applied on TI’s DSP and wireless products. Recently, his work includes defining technology for 45nm and 32nm for ASIC, DSP and wireless products. His research, development and application interests include interconnect modeling, variability, DFM and new architectures for digital and analog products. He has served on Technical Program Committees for DAC, CICC, VLSI Design and ISQED. He received B.E. from UVCE, Bangalore University and Ph.D. degrees from University of Texas at Dallas.

Palkesh Jain, Texas Instruments India

Palkesh Jain graduated from the Indian Institute of Technology (IIT) Bombay in July 2004, with Bachelors and Masters in Electrical Engineering, under the Dual Degree Programme. His Masters research was on Soft Errors. He joined the Reliability CAD Group at Texas Instruments India in July 2004. Since then, he has contributed to the CAD and methodology development for 65nm and 45nm reliability flows, currently leading the CAD efforts for EM and NBTI. His current research interests are in power-performance-reliability tradeoffs and SoC reliability.

Gautam Kapila, Texas Instruments India

Gautam Kapila obtained his B.E degree from NITK, Surathkal and has been with Texas Instruments for 5 years. He has contributed to Antenna, Channel Hot Carriers, Negative Bias Temperature Instability, Gate Oxide Integrity and Electrostatic Discharge CAD solutions. He contributed to FinFET reliability research, as an assignee at IMEC, Belgium. His main interests are in the areas of reliability CAD solutions, device reliability and technology. He is pursuing a Ph.D. degree in 1/f Noise study in advanced MOS devices from IIT Bombay

Madhav P. Desai, IIT Bombay

Madhav P. Desai received the B.Tech. in Electrical engineering from IIT Bombay in 1984, and the M. S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.  During the period 1992-1996, he worked in the Semiconductor Engineering Group at the Digital Equipment Corporation in Hudson, MA, where he was a Principal Engineer.  He is currently an Associate Professor in the Department of Electrical Engineering at IIT Bombay.  Dr. Desai's interests are in the areas of VLSI design and design tools, circuits and systems, and combinatorial algorithms. His doctoral work involved the study of the Simulated Annealing algorithm, which is a popular combinatorial optimization technique. While at Digital, Dr. Desai worked on timing verification, delay modeling, circuit and interconnect optimization and contributed to the design of two of the world's fastest CMOS microprocessors.

Dr. Desai has been the recipient of GTE and Schlumberger Graduate Fellowships. He has served as a reviewer for the IEEE Transactions on Circuits and Systems, the IEEE Transactions on Computers, the SIAM Journal on Control, and various conferences.

Vani Prasad, Freescale Semiconductor India

Vani Prasad received her PhD degree from IIT Bombay, India. She has been with Freescale Semiconductor, Bangalore, India since 2006, where she is currently a Design Engineer. Her research interests are interconnect design and optimization, physical design CAD and VLSI circuit design issues.

Vish Sundararaman, Texas Instruments Inc., Dallas

Dr. Vish Sundararaman is a Package Engineering Manager at Texas Instruments Incorporated in Dallas, TX, USA.  His core responsibilities include packaging readiness to support TI’s analog silicon technologies and product portfolios.  During his 8 years with TI, his major roles included thermo-mechanical modeling and analytical expertise to support advanced packaging and materials development; he has also made significant contributions to TI’s advanced CMOS silicon technologies from development through production.  Vish has a B.Tech in Metallurgical Engineering from the Indian Institute of Technology, an MS in Materials Science and Engineering from the University of Notre Dame, and a PhD in Mechanical and Aerospace Engineering from Syracuse University.  Vish packaging career began as a Post-Doctoral Research Fellow at the Georgia Institute of Technology’s Packaging Research Center.

Vidyasagar Ganesan, AMD

Vidyasagar Ganesan, manages the Soc Design at AMD, India, he has over 14 years experience in the technical management of processor development at Sun Microsystems, Texas Instruments and AMD. Vidyasagar’s interests are in technology, clocking, timing and power distribution.