Measurement Data
Measurement data
- A set of manually-measured terminal I-V from the same die of a 0.25-?m CMOS shallow-trench isolation (STI) test wafer.
- Drawn gate lengths Ldrawn = 10, 3, 1, 0.8, 0.5, 0.34, 0.26, 0.24, 0.22, 0.2 ?m (W = 20 ?m).
- The measured gate oxide thickness: tox ~ 59 Ĺ.
- The estimated LDD junction depth: xj ~ 75 nm.
- The estimated LDD spacer thickness: S ~ 120 nm.
-
For each nMOS device (Ldrawn), the following I-V data are measured:
- Ids - Vgs (0 to 2.5 V, step 0.05 V) @ Vds = 0.1 V (Vbs = 0, -0.9, -1.8, -2.7 V)
- Ids - Vgs (0 to 2.5 V, step 0.05 V) @ Vds = 1 V (Vbs = 0, -0.9, -1.8, -2.7 V)
- Ids - Vgs (0 to 2.5 V, step 0.05 V) @ Vds = 2.5 V (Vbs = 0, -0.9, -1.8, -2.7 V)
- Ids - Vds (0 to 2.5 V, step 0.05 V) @ Vbs = 0 V (Vgs = 0.5, 1, 1.5, 2, 2.5 V)
- Ids - Vds (0 to 2.5 V, step 0.05 V) @ Vbs = -2.7 V (Vgs = 0.5, 1, 1.5, 2, 2.5 V)