ROR              Rotate Right                        Flags: O D I T S Z A P C
                                                            *               *
ROR destination,count
 
                      +-------------------+
                      |  +---------------+ |  +------+
                      +-|  Destination  |-+-|  CF  |
                         +---------------+    +------+
 
    ROR shifts the word or byte at the destination to the right by the
    number of bit positions specified in the second operand, COUNT. As
    bits are transferred out the right (low-order) end of the destination,
    they re-enter on the left (high-order) end. The Carry Flag is updated
    to match the last bit shifted out of the right end.
 
    If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
    is equal to 1, the Overflow Flag is set to the XOR of the top 2 bits
    of the result.
 
  --------------------------------------------------------------------------
   Operands                  Clocks   Transfers  Bytes   Example
                           byte(word)
   register, 1                 2          -        2     ROR BL,1
   register, CL            8 + 4/bit      -        2     ROR AX,CL
   memory, 1              15(23) + EA     2       2-4    ROR WORD,1
   memory, CL           20(28)+EA+4/bit   2       2-4    ROR BYTE,CL
  --------------------------------------------------------------------------
 
       Notes:         COUNT is normally taken as the value in CL. If,
                      however, you wish to rotate by only one position,
                      replace the second operand, CL, with the value 1, as
                      shown in the first example above.
 
                      The 80286 and 80386 microprocessors limit the COUNT
                      value to 31.  If the COUNT is greater than 31, these
                      microprocessors use COUNT MOD 32 to produce a new
                      COUNT between 0 and 31.  This upper bound exists to
                      limit the amount of time an interrupt response will
                      be delayed waiting for the instruction to complete.
 
                      Multiple RORs that use 1 as the COUNT may be faster
                      and require less memory than a single ROR that uses
                      CL for COUNT.
 
                      The overflow flag is undefined when the rotate count
                      is greater than 1.

Seealso:


 RCR 
 ROL 
 RCL 
 SAR 
 SAL 
 SHL 
 SHR 
 EA 
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