INTERFACE SIGNALS

Figure 1. R6522 VIA interface Signals

RESET ()

A low reset () input clears all 6522 internal registers to logic 0 (except T1 and T2) latches and counters and the Shift Register). This places all peripheral interface lines in the input state, disables the timers, shift register, etc. and disables interrupting from the chip.

INPUT CLOCK ()

The input clock is the system clock and triggers all data transfers between processor bus and the 6522.

READ/WRITE ()

The direction of the data transfers between the R6522 and the system processor is controlled by the line in conjunction with the CS1 and inputs. When is low (write operation), and the R6522 is selected, data is transferred from the processor bus into the selected R6522 register. When is high (read operation), and the R6522 is selected, data is transferred from the selected R6522 register to the processor bus.

The eight bidirectional data bus lines transfer between the R6522 and the system processor bus. During read cycles, the contents of the selected R6522 register are placed on the data bus lines. During write cycles, these lines are high-impedance inputs and data is transferred from the processor bus into the selected register. When the R6522 is not selected, the data bus lines are high impedance.

CHIP SELECTS (CS1, )

The two chip select inputs are normally connected to processor address lines either directly or through decoding. The selected R6522 register is accessed when CS1 is high and is low.

The coding of the four Register Select inputs select one of the 16 internal registers of the R6522, as shown in Table 1.

Reg. #	RS Coding				Register Desig.	Register/Description
	RS3	RS2	RS1	RS0		Write ( = L)	Read ( = H)
0	0	0	0	0	ORB/IRB	Output Register B	Input Register B
1	0	0	0	1	ORA/IRA	Output Register A	Input Register A
2	0	0	1	0	DDRB	Data Direction Register B
3	0	0	1	1	DDRA	Data Direction Register A
4	0	1	0	0	T1C-L	T1 Low-Order Latches	T1 Low-Order Counter
5	0	1	0	1	T1C-H	T1 High-Order Counter	T1 High-Order Counter
6	0	1	1	0	T1L-L	T1 Low-Order Latches
7	0	1	1	1	T1L-H	T1 High-Order Latches
8	1	0	0	0	T2C-L	T2 Low-Order Latches	T2 Low-Order Counter
9	1	0	0	1	T2C-H	T2 High-Order Counter
10	1	0	1	0	SR	Shift Register
11	1	0	1	1	ACR	Auxiliary Control Register
12	1	1	0	0	PCR	Peripheral Control Register
13	1	1	0	1	IFR	Interrupt Flag Register
14	1	1	1	0	IER	Interrupt Enable Register
15	1	1	1	1	ORA/IRA	Output Register A*	Input Register A*
NOTE: *Same as Register 1 except no handshake.

INTERRUPT REQUEST ()

The Interrupt Request output goes low whenever an internal Interrupt flag is set and the corresponding interrupt enable bit is a logic 1. This output is open-drain to allow the interrupt request signal to be wire-OR'ed with other equivalent signals in the system.

Port A consists of eight lines which can be individually programmed to act as inputs or outputs under control of a Data Direction Register. The polarity of output pins is controlled by an Output Register and input data may be latched into an internal register under control of the CA1 line. All of these modes of operation are controlled by the system processor through the internal control registers. These lines represents one standard TTL load in the input mode and will drive one standard TTL load in the output mode. Figure 2 illustrates the output circuit.

Figure 2. Port A Output Circuit

The two Port A control lines act as interrupt inputs or as handshake outputs. Each line controls an internal interrupt flag with a corresponding interrupt enable bit. In addition, CA1 controls the latching of data on Port A input lines. CA1 is a high-impedance input only while CA2 represents one standard TTL load in the input mode. CA2 will drive one standard TTL load in the output mode.

Peripheral Port B consists of eight bi-directional lines which are controlled by an output register and a data direction register in much the same manner as the Port A. In addition, the polarity of the PB7 output signal can be controlled by one of the interval timers while the second timer can be programmed to count pulses on the PB6 pin. Port B lines represent one standard TTL load in the input mode and will drive one standard TTL load in the output mode. In addtition, they are capable of sourcing 1.0 mA at 1.5 Vdc in the output mode to allow the outputs to directly drive Darlington transistor circuits. Figure 3 is the circuit schematic.

Figure 3. Port B Output Circuit

The Port B control lines act as interrupt inputs as handshake outputs. As with CA1 and CA2, each line controls an interrupt flag with a corresponding interrupt enable bit. In addition, these lines act as a serial port under control of the Shift Register. These lines represent one standard TTL load in the input mode and will drive one standard TTL load in the output mode. CB2 can also drive a Darlington transistor circuit; however, CB1 cannot.