S3

Last updated 05/09/03

S3 is a hypothetical instruction set architecture designed with influences from the LC-2 ISA developed by Patt and Patel. It is a very simple ISA. There is no encoding for this ISA at the present time.

Memory: address space has 2¹⁶ locations (16-bit addresses), Eight 16-bit physical registers, R0-R7
All transfers from or to memory are 16 bits.
R5 is the global data pointer, R6 is the stack pointer, R7 is the link register
For this class: R0 is the return value of a function, R1 is the function’s argument (if any)
Other conventions: Programs begin at 0x3000, Stack at 0x4000, data at 0x2000

Assembly	Meaning
ADD RX, RY, RZ	RX = RY+RZ
ADD RX,RY,#IM	RX = RY+IM
AND RX, RY, RZ	RX = RY and RZ
AND RX,RY,#IM	RX = RY and IM
BRA label	PC = label
BRnzp RX,label	PC = label IF RX is negative (n) OR zero (z) OR positive (p)
JSR label	R7 = PC+1, BRA label
JSRR RX,#index	R7 = PC+1, PC = RX+index
LD RX,addr	RX = Mem[addr]
LDI RX,addr	RX = Mem[Mem[addr]]
LDR RX,RY,RZ	RX = Mem[RY+RZ]
LDR RX,RY,#index	RX = Mem[RY+index]
LEA RX,addr	RX = addr
MUL RZ,RX,RY	RZ = RX*RY
NOP	no operation
NOT RX,RX	RX = bitwise-invert(RX)
RET	PC = R7
SET RX,#IM	RX = IM
SHL RX,RY,RZ	RX = RY shifted left by RZ bits
SHL RX,RY,#IM	RX = RY shifted left by IM bits
SHR RX,RY,RZ	RX = RY shifted right by RZ bits with sign extension
SHR RX,RY,#IM	RX = RY shifted right by IM bits with sign extension
ST RX,addr	Mem[addr] = RX
STI RX,addr	Mem[Mem[addr]] = RX
STR RX,RY,RZ	Mem[RY+RZ] = RX
STR RX,RY,#index	Mem[RY+index] = RX
SUB RX,RY,RZ	RX = RY-RZ
SUB RX,RY,#IM	RX = RY-IM
TRAP #trapvec	R7 = PC, PC = MEM[trapvec<<1]

VLIW semantics

MultiOps

Instructions are grouped into MultiOps in S3. A MultiOp is a set of instructions that begin executing in the same machine cycle. All source registers in a MultiOp are read at the beginning of the cycle that the MultiOp executes. Destination registers are written depending on the Latency of each opcode. Opcode latency in S3 is 1 cycle for most operations, however true loads (LD, LDI and LDR) have a latency of two cycles.

Predication

Predicate registers are 1-bit registers used to control instruction exection. All operations in S3 have an optional predicate argument, shown as (P) before the instruction, ie

(P3) ADD R10,R9,R7

This means that the instruction only executes if the register, P3, contains a 1, else it does not.

P0 is always = 1.

Predicates are set using the cmp instruction which is a slight simplification of an instruction from IA-64:

(qp) cmp.crel.ctype pa,pb = Rx,Ry
where
qp, pa and pb are predicate registers
crel is an arithmetic condition to compare Rx to Ry (.eq, .ne, .lt, .le, .gt, .ge)
ctype is defined as follows:

		ctype
Predicate qp	Result of comparison	.unc	(blank)	.or	.and
0	0	0	nop	nop	nop
0	1	0	nop	nop	nop
1	0	0	0	nop	0
1	1	1	1	1	nop