RESUME
1. Name : TONY THOMAS E.
2. Educational Qualifications:
Degree : Bachelor of Technology (Honors) in Electronics
and Communication Engineering.
University : University of Calicut , India.
3. Personal details :
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Contact address : 12525, S. Kirkwood, Apt 336
Stafford, TX-77477.
E-mail Address : tonyt@micro.ti.com
Residence telephone no. : (281) - 240 - 3452
Office telephone no. : (281) - 274 - 2149.
Nationality : Indian.
Passport number : T 174890.
4. Work Experience:
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Currently employed as DSP Design Engineer in Texas Instruments Inc.
at Houston, TX. Working on the design and development of TI's
high performance TMS320C6X series DSPs.
The works carried out in my responsibilities so far fall into the
below mentioned areas:
* Secondary storage technology based on RAID concept and Intel
960SA RISC processor.
* LAN Terminal Servers (LTS) and Remote Access Servers (RAS) based
on 486DX-4 processors.
* Modeling in VHDL.
* ASIC development in VHDL.
5. Computer Hardware Experience:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Architectures : PCI , ISA , VESA , ATA-2.
Programmable Logic : Xilinx FPGAs , AMD MACH devices.
EDA Tools : ModelTech VHDL compiler,Synopsys,
Verilog-XL , XACT-STEP , Pearl,
Chrysalis, Orcad , Concept.
Microprocessors : PENTIUM Pro.,
Intel/AMD/TI 486DX/DX-2/DX-4,
Intel 960SA.
DSP : TMS320C6201/02/03.
Languages : VHDL, Verilog, PALASM, ASMx86,'C'.
Physical layer i/f : Ethernet , V.24 , V.35
6. SKILLS
~~~~~~~~~~~
* Sound familiarity with developing and synthesizing VHDL codes
for high speed ASICs.
* Expertise on usage of Chrysalis tools for Formal Verification.
* Sound knowledge and experience on modeling in VHDL.
* Expertise on various bus architectures like PCI,ISA,and VESA.
* Expertise on usage of AMD MACH210 devices and thorough knowledge
on design logic implementation and simulation using PALASM4.0.
* Experience in implementation and simulation of design logic in
Verilog language using Verilog-XL and Undertow.
* Expertise in implementation of system logic using Xilinx FPGAs
including the editing of Place-and-Route output of XACT-STEP6.0.
* Familiarity with usage of EDA tools like Synopsis ,Concept
and ORCAD4.4.
* Thorough knowledge on issues to be taken care in high-frequency
digital system design considering various aspects like impedance
matching using various types of termination,cross-talk,
clock-skew, ground-bounce, EMI/EMC and optimum routing.
* Experience in dealing with signal integrity issues in high
frequency digital systems.
* Familiarity with digital system debugging using tools like DAS,
Logic Analyzers, Storage oscilloscopes etc.
7. PROJECTS:
~~~~~~~~~~~~~
Current responsiblity: Design and development of TMS320C6X series DSPs.
Since April 1998.
Previous Projects:
(i) Design and Development of a High Speed Memory Interface ASIC
in VHDL.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Period : April 1997 - January 1998.
Location : NCR Corp., West Columbia, SC, USA.
Description :
This chip is being developed to interface 4 GB of 50ns FPM DRAM
with a Memory Controller ASIC in an 8-way multiprocessing P6
Processor based system. By employing a dual-interleave memory
architecture, the chip is optimized to support zero wait state
data transfer at upto 100 MHz clock across a 72 bit data bus and
the memory modules.
* Uses the 0.35 micron technology from VLSI.
* An 18K gate design.
* The maximum through-put calculated for the memory interface using
this ASIC is 800 MB/sec.
Team size : 1
(ii) Design and Development of a Fast Page Mode DRAM model
in VHDL.
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Period : February 1997 - April 1997.
Location : NCR Corp., West Columbia, SC, USA.
Description :
This model was developed for the simulation and debugging
of a Memory Controller ASIC designed for an 8- way multiprocessing
P6 processor based system. With its advanced features and highly
compact logic this model replaced the INTEL's DRAM model which
had been employed in the NCR test-benches till then.
Main features :
* Supports all standard cycles of a FPM DRAM except RAS-Only-Refresh
and Test-mode cycles.
* On-the-fly memory allocation using an architecture based on
VHDL pointers which highly reduces the memory consumption
during simulation.
* Maximum number of accessible locations practically limited only
by the size of available system memory.
* Context sensitive Data-valid-delay for read cycles which gives
the worst case timings for simulation.
* Checks for 19 types for timing violations on the input signals
based on a given set of time constraints.
Team Size : 1.
(iii) Simulation and debugging of a Memory Controller ASIC in an
8 - way multi-processing P6 Processor based system.
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Period : October 1996 - January 1997.
Location : NCR Corp., West Columbia, SC, USA.
Description :
This involved development and execution of simulation codes
in the INTEL proprietary BFM (Bus Functional Model) language for
P6 processor and verifying the various arbitration and cache-
coherency functions in the 8 - way multi-processing system being
developed by NCR.Also, the base-boards developed for this system
were debugged for design/signal integrity issues at 66 MHz
operation.
Team Size : 14.
(iv) Design and Development of a Communication Server with LTS
and RAS functionality.
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Period : August 1995 - September 1996.
Location : Wipro Infotech Ltd., Bangalore, India.
Description :
This product offers terminal connectivity with dial-in and
dial-out features permitting users to access remote LANs. It
supports a maximum of 12 Asynchronous Serial ports (V.24 at 128Kbps
full duplex), 2 Synchronous serial ports (V.24/V.35 at 256Kbps
full duplex) and one Ethernet port (AUI/ 10 BASE-T).
H/W specifications :
* 486DX/DX-2/DX-4 , 3.3V/5V at 33MHz external clock.
* Up to 2 MB of FLASH memory using AMD29F400 / Intel28F400.
* Up to 8 MB of DRAM.
* CL-CD2231 Remote Access Communication Controller with Bus Mastering
capability and support for Data Link Layer protocols viz. PPP,SLIP,
HDLC and MNP.
* 85C30 synchronous communication controller chip for Synchronous
serial interface.
* National DP83902 Ethernet Controller chip.
Personal Contribution :
Involved in :
(1) Basic design/architecture freezing of the hardware.
(2) Implementation of the design logic in PALASM/Verilog.
(3) Fitting and functional simulation of the PALASM design files
in AMD MACH210 using PALASM4.0.
(4) SYNTHESIS of Verilog design files using SYNOPSIS tools.
(5) Mapping, Placement and routing of synthesized design files
targeting XC3142 FPGA as well as manual editing of the Place
and Route output using XACT-STEP6.0.
(6) Timing Simulation of the logic using Verilog-XL and Undertow.
(7) Schematic entry using ORCAD4.4 / Concept tools.
(8) Placement of Components for PCB CAD using Allegro tools.
(9) Development of the S/W required for testing the functionality of
the board in ASMx86 language.
(10) Debugging and testing of the H/W using equipment like Storage
Oscilloscope, Logic Analyzer etc.
(11) Monitoring the EMI/EMC tests for FCC/CE compliance of the
product at a certified agency.
Position : Project Engineer.
Team Size : 3
(v) Design and Development of a RAID (level-3) Controller PCI
add-on card.
--------------------------------------------------------------
Period : November 1994 - July 1996
Location : Wipro Infotech Ltd., Bangalore, India.
Description :
This product supports up to 10 Enhanced IDE disk-drives
(8 data drives and 2 Parity drive) which can configured in any
one of the RAID levels 0,1,or 3. On-the-fly parity generation/data
rebuild algorithm was implemented in H/W to enhance the performance
of the system.
H/W specifications :
* Intel 960 SA RISC processor running at 16 MHz.
* PLX 9060 Bus Master Interface Chip for PCI interface compliant with
PCI 2.1 specifications.
* 128k FAST SRAM.
* 128k FLASH memory.
* 9 AMD MACH210-7 devices for implementing the board logic.
* Xilinx XC3090 FPGA for implementing the Parity generation/Data- rebuild
algorithm.
* Support for 5 Enhanced IDE channels in PIO Modes 0,1,2 and 3 as well as
Multi word DMA mode.
Personal Contribution :
Involved in :
(1) implementation of the board interface and arbitration logic in AMD
MACH210s. PALASM3.0 s/w was used for the fitting and simulation
of the design files for MACHs)
(2) Development of the Monitor program for debugging and testing of the
H/W functionality in i960 assembly language.
(3) Schematic entry using ORCAD3.0.
(4) CAD support.
(5) Debugging and Testing of the H/W
Position : Project Engineer
Team size : 3
(vi) Design and Implementation of a Distributed Computing System
on DOS PCs.
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Period : January 1994 - August 1994.
Location : Regional Engineering College, Calicut, India.
Description :
The software for this system was completely developed
in 'C' and it was done as part of B.Tech course curriculum .
This involved setting up of a star-configured PC network
using special communication cards and development of a sub-system
which supports Process Distribution and Inter-Process-Communication
running over DOS in the user PCs as well as a switching software
which controls the traffic running in the central routing machine.
Main features :
* Supports forking of processes and inter-process communication
which involves transferring duplicate copies of the code, data
and stack segments of the parent process to idle PCs in the
network and returning different IDs to the parent and the child
processes there by enabling them to execute different threads.
* File transfer facilities which enables the users to transfer
files across different PCs in the network.
* TALK facility similar to that in UNIX based systems which
enables the users to talk online.
Team size : 5
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