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VLSI DESIGN & TEST WORKSHOPS 6^thIEEEVLSI Design & Test Workshops August 29-31, 2002 Bangalore, India Sponsored by VLSI Society of India In Cooperation With: IEEE-CS-TTTC IEEE EDS/SSCS Bangalore Chapter (Confirmation Awaited) http://vlsi-india.org Related Site: http://vlsi.ccrl.nj.nec.com

History:

Workshop Title	Venue	Date	Partici-pants
1^st VDAT	Chennai	January 7, 1998	30
2^nd VDAT	New Delhi	August 6-7, 1998	70
3^rd VDAT	New Delhi	August 20-21, 1999	120
4^th VDAT	New Delhi	August 25-26, 2000	150
5^th VDAT	Bangalore	August 16-18, 2001	220

Topics of Workshops:

The following workshops will be held concurrently:

Workshop on High-level Design will discuss issues related to system-level synthesis, embedded systems, codesign, core-based design of SoC, timing convergence, high-level synthesis, logic synthesis, memory synthesis, and FPGA synthesis.

Workshop on Physical Design and VLSI Technology will discuss all issues related to physical aspects of integrated circuits, such as layout, fabrication, packaging, opto-electronic circuits, MEMS.

Workshop on Testing and Verification will discuss issues related to testing, testability, and verification of digital designs, memories, analog designs, and mixed-signal designs.

In addition, VLSI Education Day (VED 2002) will be held as part of VDAT 2002, on August 29, 2002.

Conference Committee

General Chair:

C.P. Ravikumar, Texas Instruments India

Technical Program Committee

Vishwani Agrawal, Agere Systems, USA

Jagannathan Balaji, Purple Vision Technologies, India

M. Balakrishnan, IIT Delhi, India

Ashok Balivada, National Semiconductors, India

Navakant Bhat, IISc, Bangalore

Bhargab Bhattacharya, ISI Calcutta, India

P. Chakrabarti, Banaras Hindu University, India

P.P. Chakrabarti, IIT Kharagpur, India

Srimat Chakradhar, NEC, USA

Anil Gundurao, Cypress Semiconductors, India

S. Karthik, Analog Devices, India

Anshul Kumar, IIT Delhi, India

S. Mahant-Shetti, KARMIC, India

Durga Misra, NJIT, USA

N.S. Murthy, Philips, India

Dipankar Nagchoudhuri, IIT Delhi, India

S. Nandi, IIT Guwahati

R. Parekhji, Texas Instruments, India

S. Ramesh, IIT Bombay, India

C.P. Ravikumar, Texas Instruments, India

G.H. Sharma, United Telecom Ltd., India

Narendra Shenoy, Synopsys, India

Vinay Shenoy, Philips Semiconductors, India

S. Sherlekar, Sasken, India

Alok Singh, Virage Logic, India

P. Sridhar, Controlnet, India

M. Srivas, Realchip, India

S. Srinivasan, IIT Madras, India

V. Visvanathan, Texas Instruments, India

ADDRESS FOR CORRESPONDENCE

Authors should submit extended abstracts for talks, proposals for embedded tutorials (1 hour or 2 hour duration), and proposals for panel discussions or special sessions, to:

C.P. Ravikumar

APDC, Texas Instruments, India

Wind Tunnel Road, Murgeshpalya

Bangalore 560017

Email: cpravikumar@rediffmail.com

FAX: 91-80-5269456

If submitting by email, authors must use ASCII text, PDF, or postscript format.

For online submissions, click here.

IMPORTANT DATES

Last Date for submission: March 30, 2002

Notification of acceptance: May 15, 2002

Last day to received final manuscript: June 1, 2002

Workshop Dates: August 29-31, 2002

NOTE: The workshops are a forum to promote research and development in all aspects of VLSI in India. Authors of accepted papers will not be required to submit full papers, although they are encouraged to do so. All authors of accepted papersm must submit presentation foils of their talks in powerpoint or PDF format. Final submissions (full papers or presentations) will be available as Workshop Proceedings. Papers presented in the workshops may be revised and published/presented in other forums.