Table of Contents
The Virtual Wafer Fab Technology for the Deep-Submicron
ULSI Era
The ULSI Era: Technology Scaling
PPT Slide
VLSI Design and Manufacturing Hierarchy
Multi-Level Representation
Layout + Process = Chip
New Technology Development
The Microelectronics Industry
Chip Design and Wafer Fabrication (Design–Manufacturing–Characterization–Simulation–Verification)
Virtual Wafer Fab
Project DOUST
Major Objectives
Three Major Goals
Overall Planning
Multi-Variable Design Space Multi-Target Optimization
Process and Device Database
Projection and Contour Plots
Conceptual Database
Conceptual Framework
Methodology of Implementation
Threshold Model Based on TCAD
Research ? Development ? Application
Summary: Strategic Factors |
Author: Xing
Zhou
Email: exzhou@ntu.edu.sg
Home Page: http://www.ntu.edu.sg/home/exzhou/Research/DOUST/intro.htm |