Design of FIR Filters for Low Power Applications.A Shyamprakash, Cadence Design Systems, Ram G Mohan, IIT Delhi
Parameterized Divider Cells for Datapath SynthesisRohit Sharma, Texas Instruments India.
Standard Cell based and FPGA based ASIC design of CORDIC coreA. V. Pranatarthi, ICON Systems, India
HardWare Software Partition Using Genetic Algorithms and Application to MPEG Encoder and ECHO CancellationC. Mandal, R. Zimmer. Brunel University. UK
Integrated Scheduling and Allocation for Synthesis of Structured Data Path.Yosef Gavriel, Department of Computer and Electrical Engineering, Virginia Tech, Blacksburg, VA
Constraint Programming Applied to High-level and System level Sythesis of Application-Specific Systems.N.R. Alamelu,PSG College of Technology ,Coimbatore, India
Modelling and Performance Analysis of Buffered Leaky Bucket Policing for ATM Networks using VHDL.M. Karthik, H. Narayanan, IIT Bombay, India.
Development of a Large Scale System Partitioner.A. Srivastava, S. Gupta, C.P. Ravikumar, IIT Delhi and Chandrashekhar,CEERI, Pilani
System Partitioning and Technology SelectionV. Sahula, IIT Delhi.
VLSI Design Flow ManagementS. Chakraverty, Delhi Institute of Technology, India.
Hardware-Software Cosynthesis of a MultiProcessor System for Real Time Application.Sanjeev Sablok, Dinesh Kumar, Anil Vohra, P. J. George, Kurukshetra University.
ALLIANCE Based VLSI designM. Mahendale, Texas Instruments, India.
Invited Talk on Design of Ankoor Digital Signal rocessor
M-Testable Arithmetic Iterative Arrays.Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer. Mentor Graphics.
Automated Synthesis of Large Phase Shifters for BIST.Rubin A. Parekhji, Texas Instruments.
On Connectivity and Inversion Problems in Scan.Ashok S. Nale, Silicon Interfaces.
DEST: A Method for Multiplr Stuck-at and Delay FaultDetection in Combinational CircuitsShekhar Saha, Synopsys (India).
Methodology for Static Verification of Multi-Million Gate Design.Ashima Malhotra, Duet Technologies and C. P. RaviKumar, IIT Delhi.
Multiple Signature Testing for Path Delay Faults.Chandramouleeswaran, Texas Instruments India.
Integrated Test Vector Flow for Design QC.S. Baskar, Texas Instruments India.
Test Vector Language Parser, enabling language independent test flow.A. Sinha, P. Kaul and C.P. Ravikumar, IIT Delhi.
Designing a Testable IIR Filter Core.V.C. Prasad, IIT Delhi.
Fault Diagnosis of Analog Circuits : A Review (Invited)V.C.Prasad, IIT Delhi and N.S.C.Babu, Department of Electronics, Delhi.
Test mode selection for Analog fault diagnosis using dictionaryS. Balajee, Texas Instruments
Tutorial on Design to Test Environment.
A Fast Algorithm for Transistor Folding.R.K. Pal, S.P. Pal and A. Pal, University of Calcutta.
Wire Length Minimization in Multi-Layer Channel Routing.Sacheendra Nath and C.P.RaviKumar, IIT Delhi.
Crosstalk Minimization through Transistor Sizing.Debashis Sarkar, Motorola India Electronics Ltd. and B. B. Bhattacharya, ISI Calcutta.
Fast Circuit Extraction from MOS switch Level Descriptions.Soumendra Nath Mandal and Anurag Seth, Duet Technologies.
Effective Capacitence Seen by Timing Arcs in a Cell.P. Mahalingam, S.C. Nandy, B.B. Bhattarchaya ISI Calcutta and S. Sur-Kolay Jadhavpur University.
Topological Routing in the Presence of Polygonal Obstacles.Rajeevan Chandel, REC Hamirpur.
Dielectric Based Electrostatic Microactuators.R. Krishnan, Cypress Semiconductors, India .
TTL/CMOS interfacesPreeti Gupta, Synopsys India.
Place Algorithm for Low Power.Susmita Kar-Kolay, Jadhavput University.
Tutorial on Special Topics in VLSI Layout.Satrajit Ghose, ISI Calcutta, S. Sur-Kolay, Jadhavpur Univ. and B.B. Shattacharya, ISI Calcutta.
VLSI Chips on 3-D Closed Surfaces.K. Rajagopalan, Analog Devices (India).
Reliability Problems in Deep Submicron ICs.
Logic Design Workshop
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Abstract
In this paper , the system is mapped to a Processor and Hardware
Architecture. To do such a mapping , the system has to be partitioned into
tasks which are categorized into software and Hardware units. The tasks
which come in the software units are those which take some form of user
input , are executed on the processor(which is available off the shelf)
and the time consuming tasks like signal processing transforms , matrix
transformations, matrix inverse are to quote a few come in the hardware
partition.
We have proposed a novel approach to the partitioning using Genetic
Algorithms. The input to the partitioning process, are the tasks involved,
in the system which is to be designed. The next input, are the various
implementations which are possible for each of the tasks. The first information
is usually obtained through data flow / task graphs for the system.
The task graph is an directed acyclic graph in which the nodes represent
the tasks which are identified in the system and the directed arcs represent
the scheduling information. The metrics of a particular task are the time
of execution, and the cost of the task as per the implementation which
is either Hardware or software.
Abstract
Download postscript version of paper
Abstract
Important goals of data path synthesis techniques are to minimize
the cost of the data path and to maximize its performance. At this level
of design, the performance is measured in terms of the number of time steps
in which the data dependency graph of operations is scheduled. There are
two important steps in data path synthesis: scheduling of operations and
allocations of hardware resources. Scheduling directly determines the performance
of the design and places a lower bound on the cost of the data path. Allocation
directly determines the cost of the data path and places an upper bound
on the performance of the design. In the earlier stages of development
the two steps were done separately. Now they are generally done simultaneously
to produce better global results.
Ultimately all the components in the synthesized data path need to be placed and their interconnections routed. Some of the current data path synthesis techniques produce data paths where the interconnection between the components is random; some other techniques produce bus based structures. Data paths with random interconnects tend to impose a penalty during placement and routing. Bus based data paths, on the other hand, could have more buses than the maximum number of concurrent transfers in any time step. Since buses are generally relatively long distance interconnects, the space taken up by these is under utilized when there are more buses than transfers generally taking place. To account for these considerations we have developed a genetic algorithm to support the synthesis of structured data paths. The aim of the system is to produce designs with a simple and predictable layout structure. These structures conserve on-chip wiring resources. The data path is organized as architectural blocks (A-block). Each A-block has a local functional unit (FU), local memory elements and internal interconnections. Besides the A-blocks there are one or more global memory units and only a few global buses interconnecting the A-blocks and the global memory units.
Our scheduling algorithm delivers a performance and hardware cost optimized schedule for a given partial order of operations. The schedule is such that the architecture required to satisfy it is of relatively low cost and satisfies a minimum performance constraint. The scheduling is guided by user specified architectural parameters such as the number of A-blocks and global buses. The scheduling algorithm is versatile enough to handle multi-cycle operations and multiple implementations of an operation. The advantage of our method over existing methods is that random long-distance interconnects between data path elements are avoided. This feature makes the technique especially attractive for the high-level synthesis of designs which are intended to be implemented on reconfigurable architectures and programmable structures such as an FPGA, where interconnect resources are limited. Our method has been applied to standard examples. The resulting data paths compare favorably with other techniques for data path synthesis, in terms of performance and data path cost, while at the same time they have a structure that is advantageous for placement and routing.
Abstract
Asynchronous Transfer Mode (ATM) is the transfer mode of choice
for Broadband Integrated Services Digital Networks (B-ISDN). In ATM, a
call can exceed the negotiated traffic parameters up to maximum capacity
of User Network Interface (UNI) and therefore a new network function called
Usage Parameter Control (UPC) or policing function is to be implemented.
The leaky bucket shapes the traffic close to its negotiated Quality of
Service (QoS) parameter within a relatively small time constant. This paper
discusses the implementation of Leaky Bucket mechanism with input data
buffer using VHDL.
Abstract
Partitioning is the technique of breaking up a large system into
several smaller interacting components. In short, it is a method of divide
and conquer that is used to reduce the size of the problem. Rapid advances
in VLSI Technology, and the corresponding increase in system complexity
have necessitated the development of efficient tools for system partitioning.
These find application in VLSI layout and floor planning, reducing the
component count and the number of interconnects for multiple-FPGA prototyping
of systems, etc.
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Abstract
The number and diversity of VLSI/CAD design tools has increased
almost at the same pace as the the complexity and size of chip designs.
There has been an increasing need for CAD management tools that can help
manage design process/flow. A design-flow manager is a tool that helps
the design team in organizing, monitoring, and automating the design process.
We shall provide a tutorial overview of recent work in the area of design
flow management. We review the characterstics and features of several flow-management
tools. We indicate the need to incorporate hierarchy and concurrency into
flows. We summarize the impact of modern technological breakthroughs on
in flow management.
Abstract
This paper describes the design efforts centered around ALLIANCE:
A set of VLSI cad tools. The behavioral description for the system ( 2
to 4 line decoder is written in VHDL. Using simulator tool ASIMUT, the
VHDL source code is validated and simulated. A pattern file is then generated
using a pattern generator, GENPAT. The core of the chip is defined and
then using LOGIC tool the standard cell mapping is done. Then using the
net-list optimizer tool NETOPTIM, the fanout problems are removed within
a net-list and delays are optimized. Through SCR (Standard Cell Router)
tool router routing is done and physical design layout is obtained. The
design errors can be checked by using a design rule checker. Design for
a 2 to 4 line decoder was obtained using the above package.
Abstract
The talk will cover challenges in designing a new DSP core, based
on our experiences with Ankoor (TMS320C27xx) - the next generation DSP
core designed at TI India. We will present 3 important aspects of the design
process -
Architecture Development
We will show how an architecture is influenced by various factors
including application domain characteristics, requirements of the application
development environment and the target silicon technology.
Functional Verification
We will present a comprehensive verification methodology that addresses
the following questions :
The talk will conclude by pointing out some of the opportunities
and the challenges for the future.
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**Multi-dimensional: (area-delay-power-test-reliability-manufacturability)
Abstract
An M-testability concept is presented as a further development of
C-testability , to cope up with iterative arrays of non-identical cells,
regardless of the fault type. M-testability is proposed, based on a developed
Classified-Level Approach (CLA), applied to interconnected cells as a first
step towards their test-vector prediction. These vectors, determined using
an elaborated Variable Testability Measure (VTM), are compacted for the
entire array. M-testability is experimented on various arithmetic arrays
and interesting results are obtained.
Abstract
Download PostScript Version of Paper.
Abstract
The Static Verification approach is not based on functional vectors.
Thus it typically runs very fast and can handle multi-million gate designs.
Static Verification also gives 100% coverage of the design, in that every
path in the design is checked for functionality and timing. This approach
involves using two different tools to break the verification problem. A
static timing analysis tool is used for timing verification. And a formal
verification--in particular a equivalence checker--tool is used for functional
verification. Used together, static-timing analysis and equivalence checking
deliver exhaustive coverage of timing critical paths and functional equivalence
for system-level designs at speeds that are orders of magnitude faster
than gate-level simulators. This paper discusses the methodology for using
static verification in the ASIC design cycle flow. It also shows with the
help of an example how static verification could achieve a reduction of
90% in verification runtimes with respect to simulation.
Abstract
ashimam@duettech.com Ashima Malhotra, Duet Technologies rkumar@ee.iitd.ernet.in C. P. RaviKumar, IIT Delhi.
Abstract
Testability plays an important role in the design of reusable cores.
In this paper, we consider the design of a testable core of a DSP application,
namely, an infinite impulse response filter. The core that we designed
can be used as a building block in the construction of a ladder-type IIR
filter network. We used the multiple signature built-in self test technique
to make the core self testable. We shall present the testability measurements
made on the IIR core.
Abstract
In this paper we describe the design of a high performance, language
independent parser kernel. We also discuss the need for such a parser kernel,
and how it aids in architecting a VLSI test flow that is System On a Chip
(SOC) ready.
Test vector languages are crucial interface languages for passing
device information and test vectors from the post-design flow onto the
ATE floor. As the design complexity scales the Moore's law curve, aided
by the embedding of pre-designed cores onto a silicon wafer; the number
of test vectors increase sharply. This warrants the use of high performance
test EDA tools for test vector manipulations. The heart of all these tools
is the test vector language parser kernel, whose performance plays a key
role in determining the performance of the tools embedding the parser kernel.
As SOC becomes more pervasive in usage, different core's test information
and the vectors come from different sources. The EDA tools need to have
the capability to handle multiple test vector language formats. This is
handled by the parser kernel. Thus this parser kernel plays a key role
in moulding the VLSI test flow to be SOC ready.
Abstract
There are three broad classes of methods for fault diagnosis of
Analog circuits.They are called (i) fault analysis (ii) fault verification
and (iii) fault dictionary. Fault analysis involves determination of values
of all components of the circuit under test.This requires generation of
as many eqations as there are components using test measurements.Further
these equations have to be independent.This is usually very time consuming.Fault
verification assumes that only a fixed number (say, K )of elements are
faulty.However it is not known which set of K elements out of N elements
of the network are faulty.Fault verification methods determine the set
of K elements which are likely to be faulty and then compute the values
of these elements .Fault dictionary approaches use a look table, often
called dictionary to isolate a fault.Such a table has predetermined faults
as rows and expected measurements values as columns.By "matching" the actual
measurements with expected measurement a fault can be identified.
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Abstract
With increasing shift on System-on-chip, it is very important to
have a integrated design to test framework in order to reduce overall test
program generation cycle time. This tutorial will discuss the framework,
which maps the design data to test environment seamlessly.
Abstract
The objective of transistor sizing is to reduce the circuit delay
by increasing the area of transistors. One by-product of transistor sizing
is the generation of layouts of transistors of widely varying size. In
row-based layout synthesis, we group pMOS and nMOS transistors together
and place them in rows. The layout area for these designs is wasted due
to non-uniform cell heights. The layout area required can be reduced by
folding large transistors so that their height is reduced. Her and Wong
have developed an O(m^6) dynamic programming algorithm for the general
transistor folding problem. (If only s heights are possible for the folded
transistors, the complexity of Her and Wong's algorithm is O(m^3s^3). In
general, s is O(m).) Kim and Kang have developed a more practical algorithm
for the case of row-based designs. The complexity of their algorithm is
O(m^2 log m) or O(s(m+s) log m). They also show that the area of row-based
designs can be reduced by as much as 30% by performing transistor folding.
In this paper, we consider the row-based-design transistor-folding problem
and develop an O(m^2) or O(s(m+s)) algorithm to minimize area. Not only
is our algorithm asymptotically faster than the algorithm of Kim and Kang,
it is also conceptually simpler. We also report on experiments conducted
by us that show that our algorithm actually runs much faster than the algorithm
of Kim and Kang. Our experiments indicate that our algorithm runs 3 to
50 times as fast for m values in the range [100, 100,000].
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Abstract
In this paper a simple and effective method for calculation of Effective
capacitance for the PI admittance seen by a timing arc of a cell has been
presented. With technology moving into deep submicron level, propagation
delay and the output slew over the timing arcs of cell can no longer be
calculated without taking into account the resistive component of the interconnect.
The algorithm finds the effective capacitance by matching the output slew
characterizing the waveform. The capacitive load so found takes care of
resistive component of the load seen by the timing arc. For the given slew
equation of a timing arc, a simple electrical model for the timing arc
is found as a function of input slew and output capacitance. Waveform for
the given PI admittance is matched to obtain the effective capacitance.
The paper also gives an overview of different methods for calculating ceffective.
The algorithm presented here is an iterative one. In the course of the
paper, improvement of the algorithm has been sought and the whole process
boils down to three calls to slew equation. The algorithm is capable of
dealing with slew information provided in a timing library, irrespective
of the form whether it is provided in the raw tabulated format or in form
of equation. The procedure has been integrated in the RSPF-based delay
calculation flow of Duiet's DCL-based delay calculator. Finding Ceffective
becomes indispensable for achieving high degree of accuracy in delay calculation
specially when delay and slew are characterized as a function of input
slew and pure output loading capacitance. Ceffective value calculated by
using the characterized tabular data and the corresponding Pi admittance
are used in the SPICE-netlist and the high degree of accuracy is observed
in the simulation result. As the ASIC vendors usually characterize the
cells as a function of input slew and output capacitance current algorithm
applicability for high degree of accuracy. This paper also addresses incorporation
of Ceffective based flow in DCL-based flow. DCL(Delay Calculation Language)
is the Procedural Interface based language for writing delay and power
informations.
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Abstract
A micro-actuator is a silicon micro-mechanical transducer designed
to perform a specific actuation function on application of an external
signal. In this work silicon Dioxide based cantilevers form the basis for
the microactuators. The released Silicon Dioxide cantilevers are straight,
strong and show less fatigue.The use of insulator also permits greater
flexibility in design . The Silicon Dioxide beams are metal coated to make
them conductive to the electrostatic potential. Direct wafer bonding technology
has been used to get the etch-stop layer and precise pit depth using bulk
micro-machining of Silicon. The general advantage of this technique is
an accurate control of actuator dimensions and versatility in the choice
of beam materials. The cantilever beam microactuators are a stepping stone
for a couple of microactuators.It can be utilized for a micro-switch, which
has low power dissipation, low 'on'' resistance than conventional transistors
and small size, light weight and higher operational frequency than electro-mechanical
relays. These microactuators have rugged and shock-proof nature and highly
suitable for space launch vehicles and in vibrant situations.
Abstract
Conventional placement techniques speak of speed and delay as the
consideration factors. In this work, the cost of the Simulated Annealing
algorithm has been modelled by a new approach to optimize the power dissipation.
The cost function considers the switching activity of the nets in addition
to their capacitance. The results were measured and compared for conventional
and power-optimized placements. The Low Power Placement algorithm was run
on standard cells for several static CMOS combinational circuits and the
results found to be quite encouraging.
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