VDAT 2004 : Technical Program

Time	Description
8.00 to 9.00 AM	Registration
9.00 AM	Inauguration. Venue – Mahatma Gandhi Auditorium, Infosys Leadership Institute
9.15 AM	Session D1-Keynote Talk by Prof. Dinesh Sharma of IIT Bombay. Venue: Mahatma Gandhi Auditorium, ILI.
10.15 AM	Tea Break
11.00 AM	Session D1-Tutorial Venue – Room Subhash Chandra Bose		Session D1-Education Venue – Room Bhagat Singh
	Jagdish Rao, Texas Instruments, India. VLSI Design Challenges to Enable SoC. Tutorial.		Shekhar Pradhan and Felica W. Blanks, Bluefield State College, West Virginia, USA. The Role of Institutional Development and Advancement Office in Promoting Undergraduate VLSI Education - A Role Model Concept
			Vineet Sahula, MNIT Jaipur. VLSI Curriculum in an Indian University.
			Mini Panel Discussion – Student Projects in VLSI: Is a Change in Perspective needed? Experts from the field of VLSI will debate on this topic.
1.00 PM	Lunch and Time to Visit Exhibits. Exhibits will be located in Room Ashoka
2.00 PM		Session D1-FNAQ
	Frequently Not Asked Questions! Expert panelists will answer questions from the audience. Technical questions can be sent to ravikumar@vlsi-india.net
3.30 PM	Tea and Time to Visit Exhibits
4.00 PM		Session D1-Panel Venue – Mahatma Gandhi Auditorium
	Taking VLSI Education to the Next Level of Competence. What is the need of the hour today – quantity or quality? Several M.Tech programs on VLSI and Embedded Systems have been started in the country and short-term training programs in these areas are being offered by training institutions. Do we now have the critical mass? Is the training being provided adequate? How can we take hi-tech education to the next level of competence? How can educational institutions, industry, and governmental organizations synergize towards this cause?Expert Panelists will debate on this topic. The names of the panelists will be announced.
5.30 PM	Session D1-Poster-1 FPGA Applications Venue – Subhash Chandra Bose	Session D1-Poster-2 Logic Design Venue – Room Bhagat Singh	Session D1-Poster-3 Systems Design Venue - Room Chanakya
6.30 PM	Break for Dinner

Day 2 : August 27, 2004

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Time		Description
	Advance Program for Day 2
9.00 AM		Session D2-Keynote1
	Keynote Speech -"Challenges in growing high-tech organizations in India - Infosys Perspective" by K. Gopalakrishnan, Infosys. Venue – Mahatma Gandhi Auditorium.
10.00 AM	Tea and Time to Visit Exhibits
10.30 AM	Session D2-EDA Venue – Room Subhash Chandra Bose	Session D2-Analog Venue – Room Bhagat Singh	Session D2-Test Venue – Room Chanakya
	Shabbir H. Batterywala, Synopsys (India) Pvt. Ltd., Narendra V Shenoy, Synopsys Inc., Richard Rudell and Nidhi Sawhney Parallelizing a Statistical Capacitance Extractor	M. Shankaranarayana Bhat, NITK Surathkal, Rekha S. and Jamadagni H S., IISc, Bangalore Design of Current-mode CMOS Multiple- valued Latch	Sarath Kumar Reddy, Ravi Dasari, Mentor Graphics India, Venkata Rangam, TI India. An ATPG Approach for 2-D Array Configurable Logic Structures
	Subhashis Mandal, Abhishek Somani, Shamik Sural and Amit Patra, IIT Kharagpur and Robert Drury, National Semiconductor, Santa Clara, USA. A Connection Graph based Variable Wire Width Approach to Analog Routing	G.Suresh, G.L.Biswas, K.D.N.V.S.Prasad and A.T.Kalghatgi. Configurable I/Q Modulator using Cordic based DDS Architecture.	Shantanu Gupta, Santanu Chattopadhyay and Tarang Vaish, IIT, Guwahati. A Novel Approach to Reduce Test Power Consumption
	Sreekanth K.M., Lionel Dahyot Vinod Kumar. Texas Instruments India Ltd. Novel Approach to Solve IP Integration Problems in an Era of SOC.	M. Shankaranarayana Bhat, NITK Surathkal and Jamadagni H S., IISc, Bangalore Design of Current-mode Flash ADC	Susanta Chakraborti, Pradyut Sarkar and Arindam Karmakar, University of Kalyani. Fault Diagnosis by Spectral Method
12.00 Noon		Break
12.15 PM	Session D2-Crosstalk Venue – Room Subhash Chandra Bose	Session D2-Circuits Venue – Room Bhagat Singh	Session D2- Validation Venue – Room Chanakya
	A. Ravishankar and Aniket Singh, IIT Madras. Maximization of Aggressor Influence in Crosstalk-Delay Testing	Anil V Nandi, BVBCET, Hubli, Saumen Das and S.K.Lahiri, IIT, Khargpur. Development of Silicon Piezoresistive Accelerometer for Avionics Applications+	N.Vijayaraghavan and Dimple Lalwani, ST Microelectronics Ltd. Automated Silicon Debugging Methodology for Validating Standard Cells.
	Sachin Shrivastava and Sreeram Chandrashekhar, Texas Instruments, India. Crosstalk Noise Analysis at Multiple Frequencies	Sunil Kumar Vashishtha, Intel India Tech Pvt Ltd, Bangalore and Basbi Bhaumik, IIT Delhi. Design of 1.5V, 10-bit, 1200 mV Input range, CMOS, Pipelined Analog-to-Digital Converter.	Subhashis Mandal, Siddhartha Mukhopadhyay, Amit Patra and Santosh Biswas, Advanced VLSI Design Lab , IIT Kharagpur. A Formal Approach to On-Line Monitoring of Digital VLSI Circuits.
	Sushrant Monga, Paras Garg and Frederic Hasbani. ST Microelectronics. A Mathematical analysis of analog and digital summation tecniques in compensation block for I/O buffers.	Venkatesh C. and Navakanta Bhat, IISc, Bangalore. A MEMS Oscillator based on displacement sensing principle.	Subash Chandra Bose, CEERI, Vishal Gupta and Dinesh Jain BITS, Pilani. Fault Observability Analysis of CMOS Op-amp in Frequency domain.
1.00 PM	Lunch and Time to Visit Exhibits
2.00 PM		Session D2-Keynote2
	Ralf Pferdmenges, Infineon Technolgogies. Design Methodology for sub-0.1 um Technologies.
2.45 PM	Session D2-Memory Venue – Room Subhash Chandra Bose	Session D2-Embedded Venue – Room Bhagat Singh	Session D2-Verification-1 Venue – Room Chanakya
	Sreedhar Natarajan, Emerging Memory Technologies, USA. Emerging Non Volatile Memory: Technological Promise Or Industrial Hoax.	Atanendu Sekhar Mandal, CEERI. Designing an Embedded Processor : Specifications to Implementations.	Sunil Kakkar, Freescale Semiconductors. Advanced Processor Architectures- The Verification Challenge.
3.45 PM		Tea and Time to Visit Exhibits
4.15 PM	Session D2-Logic Venue – Room Subhash Chandra Bose	Session D2-Technology Venue – Room Bhagat Singh	Session D2-Verification-2 Venue – Room Chanakya
	P Vijayakumar and K Gunavathi, PSG College of Technology. Performance Optimization Of CMOS Circuits Using Retiming Algorithm With Stepwise Charging	Anuj Madan, Punjab Engg College, Chandigarh, Sumeet Jindal, B.Prasad and P.J.George. An Efficient Monte Carlo Device Simulator to calculate Velocity Ovesrhoot in MOSFETs.	Pritam Roy, Pallab Dasgupta and P P Chakrabarti, IIT Kharagpur. An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior.
	S. Sarkar, Rajeevan Chandel and R.P. Agarwal, IIT, Roorkee. Voltage-Scaled Repeaters for Low- Power Long Interconnections in VLSI Circuits.	Harish B.P., Srinivasan R., and Navakanta Bhat, IISc Bangalore. Process Sensitivity Evaluation of 90nm CMOS Tecnology With Gate-to-Source/Drain Overlap Length as a Device Design Parameter.	K. Uday Bhaskar, G. Chandramouli, and V. Kamakoti, IIT Madras. Parikhsa - A functional Verification Architecture for x86 Processors.
	Subhendu Kumar Sahoo, BITS, Pilani and Chandra Shekhar CERI. A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm.	Suresh Nalluri, IISc Bangalore, A.P.Shiva Prasad. Response Surface Methodology Based Design Approach for Yield Enhancement of Analog Integrated Circuits.
	Sridhar Krishnamurthy, SASTRA, Deemed University. Implementation of Advanced Encryption Standard (AES) algorithm in a resource limited FPGA.		Bhaskar Pal, A. Banerjee, P. Dasgupta, P.P. Chakrabarti, IIT Kharagpur and K. Chaitanya, Mentor Graphics, Hyderabad. A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP.
	Hande V, Uday Prabhu, Shardul Bapat, Infosys Technologies Ltd., India. Real Time Interface between Automotive ECUs and a Simulator.

6.00 PM	Session D2-Poster 1 Applications Venue - Room Subhash Chandra Bose	Session D2-Poster2 Analog Circuits Venue – Room Bhagat Singh	Session D2-Poster3 Test & Verification Venue – Room Chanakya
7.00 PM	Break for Dinner

Day 3 : August 28, 2004

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Time		Description
	Advance Program for Day 3
9.00 AM		Session D3-Keynote 1
	Keynote by Dr Sunil Sherlekar of Tata Consultancy Services
10.00 AM	Tea and Time to Visit Exhibits
10.30 AM	Session D3-FPGA Room – Subhash Chandra Bose	Session D3-Technology 1 Room – Bhagat Singh	Session D3-Test-1 Room - Chanakya
	Shaila Subbaraman, Walchand College of Engg. FPGA/CPLD Based Solution to Stretch the Speed of Microprocessor / Microcontroller Based Instrumentation.	Kanishka Biswas, S. Das, K. Dey, D. K. Maurya and S. Kal, Microelectronics Centre, IIT Kharagpur. Study of Single Crystalline Silicon (100) Surface Topography Etched in KOH Solution.	Debesh Kumar Das, Jadavpur University and Bhargab Bhattacharya, ISI Calcutta. Redundancy and Undetectability of Faults in Logic Circuits: A Tutorial.
	B. Venkataramani, G. Lakshminarayanan, M. Yousuff Shariff, T. Rajavelu and M. Ramesh, National Institute of Technology,Tiruchirappalli. Self tuning circuit for FPGA based wave pipelined multipliers.	Vinod Kumar, IIT Kharagpur. Wet Etching and Patterning of BST Film for MEMS Infrared Detector.
	Gaurav Singh Nim and B S Chauhan, IRDE.FPGA Implementation of Multiple Target Segregator.	Sudeb Dasgupta and Ritambhar Roy, Indian School of Mines, Dhanbad. Charactersiation of Gate Oxide Leakage Current of NANO-MOSFET Using Green's Function.
11.30 AM	Break
11.45 AM	Session D3-DSP-1 Room – Subhash Chandra Bose	Session D3-Technology-2 Room – Bhagat Singh	Session D3-Test-2 Room – Chanakya
	G Thavasi Raja, S. Rajaram and V. Abhai Kumar, Thiagarajar College of Engineering, Madurai. An FPGA Implementation of Code Phase Shift Keying Baseband Decoder.	Rajesh Kumar Sangati, Sowjanya Syamala and Navakanta Bhat, IISc Bangalore. Capacitance Sensing Techniques for MEMS Gyroscope.	Vishal Dalal, SASKEN Communication Technologies Ltd., Bangalore. Single Full Chip Vector for Functional Testing.
	Prashant Ramrao Deshmukh, Dr P D Polytechnic, Amravati. FPGA Implementation of Subband Image Encoder using	Srinivasan R and Navakanta Bhat, IISc, Bangalore. Reassessment of Channel Engineering in Sub-100nm MOSFETs.	Sarveswara Tammalli and Jais Abraham, Texas Instruments (India) Ltd. Hierarchichal ATPG Static Pattern Compression.
	Arun Chokkalingam, PSNA College of Engg. Implementation of Convolutional Encoder and Viterbi Decoder	Ganesan S Iyer and Rajendra M. Patrikar, Visweswariya National Institute of Technology, Nagpur. Effect on Surface Roughness on Physical Design Parameters.	D. Sharma, L. Kamath, A. Gupta, IIT Mumbai. Dynamic Error Cancellation in Fast Sigma Delta ADC. Invited Talk.
12.45 PM	Lunch and Time to Visit Exhibits
1.30 PM	Session D3-Logic Room – Subhash Chandra Bose	Session D4-DSP-2 Room – Bhagat Singh	Session D4-Power Room – Chanakya
	Chandra Mohan Umapathy, Celstream Technologies Pvt Ltd. High Speed Squarers.	Soujanna Sarkar and Subash Chandar Govindarajan, Texas Instruments, India. Embedded Tutorial : DSP Architectures.	Syed Saif Abrar, Philips. Early, Fast & Accurate Software Power Estimation for Embedded Digital Signal Processors.
	T.S.B.Sudarshan and Ganesh T.S. BITS, Pilani. Hardware Architecture for Message Padding in Cryptographic Hash Primitives.		Lakshmi Prabha Viswanathan, Government College of Technology Coimbatore and Elwin Chandra Monie, TPGIT Vellore. Power Estimation in Embedded Systems From a Pre-characterized Module Library.
	Ganesan S Iyer and Rajendra M. Patrikar, Visweswariya National Institute of Technology, Bajaj Nagar. An Application of Neural Network Learning to Physical Design Optimization in VDSM Technology.		Lakshmi Prabha Viswanathan, Government College of Technology Coimbatore and Elwin Chandra Monie, TPGIT Vellore. Dynamic Power Management in an Embedded System for Multiple Service Requests.
	Dipankar Das, Rajeev Kumar and Partha P. Chakrabarti. IIT Kharagpur. Code Compression using Unused Encoding Space for Variable Length Instruction Encodings.	Vaishali B Mungurwadi and A.S.Dhar, BVBCET, Hubli. VLSI Implementation of Viterbi Decoder.	Siddharth Tata, Siddharth Garg and Ravishankar Arunachalam, Indian Institute of Technology, Chennai. Gate Level Dynamic Power Estimation in the Presence of Varying Process Parameters.
	V. Appandai Raj, D. Jovin Vasanth Kumar, R. Madhu Karthikeyan, S. Rajaram, V. Abhai Kumar, TCE, Madurai. FPGA Implementation of OFDM Transceiver.	Mallikarjunaswamy Shivagangadharaiah Muttad, Bapuji institute of Engineering & Technology, Davangere. Ashok Rao, IISc, Bangalore and D.V. Poornaiah, IIT, Bangalore. Systolic Array based VLSI Architecture for Motion Estimation in Video Compression Applications.	Satya Sridhar Narayanabhatla, Kiran Satyamangala Jaisimha, Wipro Technologies, India and Binoj Xavier, Magma Design Automation, India. nWATT: Power Planning Methodology In Physical Design.
	Prashant Ramrao Deshmukh, DR P D Polytechnic, Amravati. FPGA Implementation of DWT Based Image Compression Coder.
3.00 PM	Tea and Time to Visit Exhibits
3.30 PM	Session D3-Panel
3.30 PM	A panel discussion will be held to discuss a topic of relevance to Indian VLSI industry. The topic and the names of the panelists will be announced.
5.00 PM	Workshop Conclusion

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Session D2-Poster 1