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VLSI Design and Test Workshops 98.

August 6-7, 1998

New Delhi, India

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Scope: To promote applications and research related to all aspects of VLSI

Sponsors: VLSI Society of India,  IEEE Computer Society Technical Committees on Test Technology
                  and VLSI (Approval Pending)
With Support From : Indian Institute of Technology, Delhi; Cadence India; Philips Semiconductors, India;
                  Texas Instruments, India

 Venue : The Habitat World, Lodi Road, New Delhi 110003

See the Registration Form
Advance Program for August 6, 1998 (Thursday)
 

Time

Test Workshop   

Chair: C.P. Ravikumar

Room: Silver Oak II

Logic Design Workshop 

Chair: Anshul Kumar

Room: Willow

Physical Design Workshop   

Chair: Bhargab B. Bhattacharya

Room: Magnolia
9:00 to 10:00 AM
Registration
Registration
Registration

Session T1

Chair :  S. Pagey, Cadence India

Session L1

Chair: Thomas Major, Philips Semiconductors

Session P1

Chair: S. Nagaraj, Texas Instruments India
10:00 to 10:20 AM M. Jamoussi, KFUPM. M-Testable Arithmetic Iterative Arrays.  Ashima Malhotra, Duet Technology and C.P. Ravikumar, IIT Delhi. Design of Digital FIR Filters for Low Power Applications. Edward Y.C. Cheng and Sartaj Sahni, University of Florida. A Fast Algorithm for Transistor Folding. 
10:20 to 10:40 AM Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer. Mentor Graphics. Automated Synthesis of Large Phase Shifters for BIST. A. Shyamprakash, Cadence India, Ram G. Mohan, IIT Delhi. Parameterized Divider Cells for Datapath Synthesis. R.K. Pal, S.P. Pal, A.Pal, University of Calcutta. Wire Length Minimization in Multi-layer Channel Routing.
10:40 to 11:00 AM Rubin A. Parekhji, Texas Instruments. On Connectivity and Inversion Problems in Scan Chains. Rohit Sharma, Texas Instruments. Standard Cell based and FPGA based ASIC design of CORDIC Core. Sacheendra Nath, C.P. Ravikumar, IIT Delhi. Crosstalk Minimization through Transistor Sizing.
11:00 to 11:30 AM
Tea Break
Tea Break
Tea Break
 
 
Time

Session T2

Chair:TBA

Session L2

Chair: TBA

Session P2

Chair: Sudershan Vuruputoor, Analog Devices
11:30 to 11:50 AM Ashok S. Nale, Silicon Interfaces. DEST: A Method for Multiple Stuck-at and Delay Fault Detection in Combinational Circuits. A.V. Pranatarthi, ICON Systems, India. Hardware Software Partition Using Genetic Algorithms and Application to MPEG Encoder and Echo Cancellation.  Debashis Sarkar, Motorola India Electronics Ltd., B.B. Bhattacharya, ISI, Calcutta.  Fast Circuit Extraction from MOS Switch-level Descriptions.
11:50  to 12:10 PM Shekhar Saha, Synopsys (India). Methodology for Static Verification of Multi-Million Gate Designs. C. Mandal, R. Zimmer.  Brunel University, UK. Integrated Scheduling and Allocation for Synthesis of Structured Data Paths.  Soumendra Nath Mandal, Anurag Seth, Duet Technologies. Effective Capacitance Seen by Timing Arcs in a Cell.
12:10 to 12:30 PM Ashima Malhotra, Duet Technologies, C.P. Ravikumar. IIT Delhi. Multiple Signature Testing for Path Delay Faults. Y. Gavriel, Virginia Tech. Constraint Programming Applied to High-Level Synthesis and System-Level Synthesis of Application-Specific Systems. P. Mahalingam, S.C. Nandy, B.B. Bhattacharya, ISI, S. Sur-Kolay, Jadavpur Univ. Topological Routing in the Presence of Polygonal Obstacles.
12:30 to 2:00 PM
Lunch
Lunch
Lunch

Session T3

Chair: TBA

Session L3

Chair: Anil Gundurao, Cypress

Session P3

Chair : Subind Kumar, Duet Tech.
2:00 to 2:20 PM Chandramouleeswaran, Texas Instruments India. Integrated Test Vector Flow for Design QC. N.R. Alamelu, PSG College of Technology. Modelling and Performance Analysis of Buffered Leaky Bucket Policing for ATM Networks using VHDL.  Rajeevan Chandel, REC Hamirpur.  Dielectric Based Electrostatic Microactuators.
2:20 to 2:40 PM  S. Baskar, Texas Instruments India. Test Vector Language Parser Enabling Language-Independent Test Flow. M. Kartik, H.Narayanan, Dept. of EE, IIT Bombay. Development of a large scale System Partitioner.  R. Krishnan, Cypress, India. CMOS to TTL interfaces in high performance VLSI circuits 
2:40 to 3:00 PM A. Sinha, P. Kaul, C.P. Ravikumar, IIT Delhi. Designing a Testable IIR Filter Core.  A. Srivastava, S. Gupta, C.P. Ravikumar, IIT Delhi, Chandrashekhar, CEERI, Pilani. System Partitioning and Technology Selection P. Gupta, Synopsys India. Placement Algorithm for Low Power.
3:00 to 3:30 PM
Tea Break
Tea Break
Tea Break
 
 
Time

Session T4

Chair: TBA

Session L4

Chair: TBA

Session P4

Chair: TBA
3:30 to 3:50 PM
Panel Discussion on VLSI Education
 V. Sahula, IIT Delhi. VLSI Design Flow Management Susmita Sur-Kolay, Jadhavpur University. Tutorial on Special Topics in VLSI Layout (Invited)
3:50 to 4:10 PM
Panel continues
 S. Chakraverty, Delhi Institute of Technology. Hardware-Software Cosynthesis of a Multiprocessor System for Real-time Applications
Tutorial continues
4:10 to 4:30 PM
Panel continues
 Sanjeev Sablok, Dinesh Kumar, Anil Vohra, P.J. George, Kurukshetra Univ. VLSI Design Experience at Kurukshetra University.
Tutorial Continues
4:30 to 4.50 PM
Group Discussion
Group Discussion
 Satrajit Ghosh, ISI Calcutta, B. Bhattacharya, ISI Calcutta, and S. Sur-Kolay, Jadhavpur University. VLSI Chips on 3-D Closed Surfaces.
4:50 to 5:10 PM
Group Discussion
Group Discussion
 Team from Analog Devices, India. Reliability Problems in Deep Submicron ICs.
Conclusion
Conclusion
Conclusion
 
 
VLSI Design and Test Workshops, August 6-7, 1998, New Delhi, India

 

Advance Program for August 7, 1998 (Friday)

Time

Test Workshop

Room: Silver Oak II

Logic Design Workshop

Room: Willow

Physical Design Workshop 

Room: Magnolia

Session T5

Chair: TBA

Session L5

Chair: TBA

Session P5

Chair: TBA
10:00 to 10:20 AM  V.C. Prasad, IIT Delhi. Tutorial on Analog Testing (Invited). M. Mehandale, Texas Instruments India. Invited Talk on Design of Ankoor Digital Signal rocessor  (Talk will discuss the architecture, logic design, and physical design of Ankoor chip).
Combined with Session L5
10:20 to 10:40 AM
Tutorial Continues
Invited Talk Continues
Invited Talk Continues
10:40 to 11:00 AM
Tutorial Continues
Invited Talk Continues
Invited Talk Continues
11:00 to 11:30 AM
Tea Break
Tea Break
Tea Break

Session T6

Chair: TBA

Session L6

Chair: TBA

Session P6

Chair: TBA
11:30 to 11:50 AM S. Balajee, Texas Instruments India. Tutorial on Design to Test Environment.
Panel Discussion (TBA)
Panel Discussion (TBA)
11:50 to 12:10PM
Tutorial Continues
Panel continues
Panel continues
12:10 to 12:30 PM
Tutorial Continues
Panel continues
Panel continues
12:30 to 2:00 PM
Lunch
Lunch
Lunch
 

Technical Program Committee

Vishwani  Agrawal, Bell Labs, Lucent Technologies, USA  
M. Balakrishnan, IIT Delhi, India  
Anand Bariya, Cadence, USA  
J. Becker, Technological University of Dermstadt, Germany  
Bhargab Bhattacharya, Indian Statistical Institute, Calcutta  
Chandrasekhar, CEERI, Pilani, India 		 Dong-Hyun Heo, Intel Corporation, USA  
Keerthi Heragu, Texas Instruments, USA  
Ajai Jain, IIT Kanpur, India  
Kozo Kinoshita, Osaka University, Japan  
Anshul Kumar, IIT Delhi, India  
Sandeep Pagey, Cadence Design Systems, India  
P. Palchaudhuri, Bengal Engineering College, India 		 C.P. Ravikumar, Indian Institute of Technology, Delhi  
Rob Roy, Intel Corporation, USA  
Manoj Sachdev, Universiy of Waterloo, Canada  
V.B.K. Sarma, University of Arizona, Tucson, USA  
Sunil Sherlekar, Silicon Automation Systems, India  
Yervant Zorian, LogicVision, USA 

Note:If you wish to organize a special session/panel at the workshop, or have any other suggestions, please contact Dr. C.P. Ravikumar, Organizing Chair of the workshop at cprkumar@india.ti.com before July 10, 1998.  The final program of the workshop will be available at the time of registration.

Registration Information:
Registration permits you to participate in any of the technical sessions, tutorials, or invited talks organized as part of the workshops.  Refreshments and lunch will be provided to all registrants at no extra charge.  Please send your registration fee through a draft  made out to VLSI Design and Test Workshops, 1998.   Make the  draft payable at Canara Bank, IIT Delhi Hauz Khas Branch.  The draft must be sent to Dr. C.P. Ravikumar, Department of Electrical Engineering,  Indian Institute of Technology, New Delhi, 110016, India.   If you wish to register on the spot,  drafts or cash  payment  in Indian rupees are acceptable.   We will not be able to accept Credit Card payments.  The current exchange rate is approximately 1 US dollar = 42 Indian rupees.

Registration Fees Before July 10, 1998
Indian Participant Foreign Participant
Academic Institution
Rs. 2000
USD. 50
Non-academic Institution
Rs. 4000
USD. 150
 
Registration Fees After July 10, 1998
Indian Participant Foreign Participant
Academic Institution
Rs. 2500
USD. 75
Non-academic Institution
Rs. 4500
USD. 175
Hotel Information:Contact numbers for The Habitat World are:+91 11 469-1920 and +91 11 469-1921.  FAX number is +91 11 460-2118.  Please ask for Ms Aarti Bhargava when inquiring about the workshops.  A limited number of rooms is available at Habitat World (Single Rooms : Rs. 1195/- per night, double rooms : Rs. 2100/- per night).  Please let us know early if you need accommodation at the Habitat World.  Habitat World can also organize tours within Delhi and to places around Delhi in a four-seater taxi if you let  them know early.  There are several Web sites that will give you information about travel and stay in New Delhi,  including www.delhizone.com.  A map showing the location of Habitat World in New Delhi is available at  www.iiefair.com/habitatmap.html .  Habitat World is located at Lodi Road, New Delhi and a pre-paid taxi from the air port to a hotel  around this area will cost Rs. 125 (About 4 US Dollars).  Prepaid taxis can be purchased at the airport itself.  Tipping the taxi driver is not necessary.  Alternative accommodation may be available in guest houses of organizations within New Delhi; you must contact the organizing chair before July 6, 1998 regarding this.  If you are a member of the program committee of  The 12th International Conference on VLSI Design 1999, please note that the meeting of the program committee is being scheduled in New Delhi on August 8-9, 1998 and you may wish to make appropriate arrangements for staying in New Delhi.

Weather Information:The weather in New Delhi in August is hot (temperatures ranging in 30 degrees to 35 degrees centigrade), with inermittent rain.  Umbrellas are recommended.

Contact Information:In case you have any questions, please contact C.P. Ravikumar (rkumar@ee.iitd.ernet.in) for clarifications.  E-mail can also be sent to cprkumar@india.ti.com up to Ju