VLSI Design and Test Workshops 2000
Final Program

August 25-26, 2000
New Delhi, India

Scope: To promote applications and research related to all aspects of VLSI
In Cooperation With: VLSI Society of India,  IEEE Computer Society Technical Council on Test Technology
With Support From : Cadence, India; ControlNet, India; Indian Institute of Technology, Delhi; Philips Semiconductors, India; RealChip, India; Texas Instruments, India; Virage Logic, India

Venue : The Habitat World, Lodi Road, New Delhi 110003

Advance Program for August 25, 2000 (Friday)

Time	Test Workshop Chair: C.P. Ravikumar Room: Casuarina	Logic Design Workshop Chair: Anshul Kumar Room: Magnolia	Physical Design Workshop Chair: Bhargab B. Bhattacharya Room: Willow
8:00 to 9:00 AM	Registration
9.00 AM-10.00 AM		Session L1 Session Chair:  Vishwani Agrawal Tapas Datta, Intel (India), Front End Design Methodology for Multi-million Gate ASICs, Invited Talk.
10:00 - 10:30 AM	Tea Break
	Session P1: Invited Tutorial Chair: Dinesh Bhatia, Univ of Cincinnati	Session L2: Design Methodologies Chair: N.S. Murthy, IBM
10:30 to 11:00 AM	Jagdish Rao, Texas Instruments (India), Physical Synthesis for Timing Convergence: Practice and Experience	Sacheendra Nath, Rupesh Shelar, and Jagmohan Nanaware, Silicon Automation Sysems. A Methodology for Automation of Design Reuse.
10.30 to 11.30 AM		Vineet Sahula, IIT Delhi. Hierarchical Concurrent Flow Graphs for Analysis of Design Processes.
11.30 to 12.00 Noon		Ajay Harikumar and  Ashutosh Tiwari, Philips Semiconductors, Bangalore. Exploring VLSI System Arhitectures.
12.00 Noon to 12.30 PM		Puneet Gupta, Mindtree and Nitij Mangal, nVIDIA. Hardware-Software Partitioning in a Reconfigurable Environment
12.30 PM to 1.30 PM	Lunch

	Session T1: Tutorial Chair: R. Parekhji, Texas Instruments	Session L3 Performance Analysis Chair: Anshul Kumar, IIT Delhi	Session P2: Current Issues in Physical Design Chair: P.R. Suresh, Texas Instruments
1:30 PM to 2:00 PM	V. Ranganathan, RealChip, System-level Testability Issues of Core-based System-On-Chip	Sirisha Voruganti, Philips Semiconductors, Bangalore. Performance Modelling (YAPI-VCC-TSS-NAPA interfaces)	P.R. Suresh, N.V. Arvind, V. Sivakumar, Chandrani Pal, and Debaprasad Das. Integrated Crosstalk and Oxide Integrity Analysis in ASIC Designs.
2:00  to 2:30 PM		Savithri, Motorola India Electronics Ltd., Advances in Static Timing Analysis.	R.K. Chauhan, S. Dasgupta, and P. Chakrabarti. Banaras Hindu University. Effect of Ionizing Radiation on the performance of NMOS inverter.
2:30 to 3:00 PM		Prashant Dubey, ST Microelectronics. Characterizing A Flip-Flop.	P. Kannan and D. Bhatia, University of Cincinnati, Performance of Routability Driven FPGA Placement.
3:00 PM to 3:30 PM		Samvit Kaul and Suneel Kumar Reddy, Philips Semiconductors, A methodolgy for high level behavioral modelling of DSPs.	Donepudi Narasayya and Srikant Reddy Modugula, ST Microelectronics. Clock distribution networks.
3.30 PM to 4.00 PM	Tea Break
	Session T2 Testing Core-Based Systems Chair: Ajai Jain, IIT Kanpur	Session L4 DSP Tutorial Chair: Tapas Datta, Intel	Session P3 Tradeoffs Chair: Sirisha Voruganti, Philips Semiconductors
4:00 PM to 4.30 PM	P.Jayakumar, Philips Semconductors, Bangalore. SOC Methodologies: COSY.	Mahesh Mehendale, Texas Instruments (India), Essence of DSP Architecture Design, Invited Tutorial.	Chandra Shekhar, CEERI, Pilani. "Leveraging Design-Abstraction Levels for Power-Performance Trade-Offs in VLSI", Invited Talk.
4.30 PM to 5.00 PM	D. Ravikumar, V. Meshram, and G. Mani, CRL, BEL (Bangalore), Test Point Insertion in Core-based Designs at RTL VHDL Specifications.
5.00 PM to 5.30 PM	Rahul Kumar, IIT Delhi. Optimization of IDDQ Test Architecture for Core-based Systems.
5.30 PM to 6.00 PM
6.00 PM	End of Day 1

 

Advance Program for August 26, 2000 (Saturday)

Time	Test Workshop Room: Casuarina	Logic Design Workshop Room: Magnolia	Physical Design Workshop Room: Willow
	Session T3 Verification  Chair: Apurva Kalia, Cadence	Session L5: Emerging Network Technologies Chair: P. Sridhar, ControlNet	Session P4 Layout Tutorial Chair: Jagdish Rao, Texas Instruments
9:00 to 9:30 AM	Amitabh Menon, Jagdish Rao, Vaideeswaran S, Bharathi V,  Texas Instruments (India), A Scaleable Verification Environment for Complex SoC Designs.	S.D. Sherlekar, Silicon Automation Systems. ADSL Chipsets. Invited Talk.	S. Sensharma and R. Pal, University of Calcutta. Wirelength Minimization in Routing and Performance Enhancement in VLSI Design.
9.30 AM to 10.00 AM	V.D. Agrawal. Bell Labs, USA. Testing in a VLSI Curriculum.
10.00 AM to 10.30 AM	Subhash Chandar G. and Vaideeswaran S., Texas Instruments (India), Addressing Verification Bottlenecks using Equivalence Checkers.
10.30 AM to 11.00 AM	Lakshmi Srinivasan, Sudhakar Surendran and Rubin A. Parekhji, Texas Instruments, India. Synchronisation Techniques for Verification of Dual Execution Stream Processors.
11:00 to 11:30 AM	Tea Break
	Session T4 Test Generation Chair:Bhargab Bhattacharya, ISI Calcutta	Session L6 System-level Design	Session P5 Memory Design Chair: G.S. Visweswaran, IIT Delhi
11:30 to 12:00 AM	Nitin Kakkar and C.P. Ravikumar, IIT Delhi. Enhanced Mutual Testing.	Pieter van der Wolf, Philips Research Labs, Eindhoven. System-level Design of Embedded Media Systems, Invited Talk.	Pratul Sharma, Amrish Kontu and  Amit Bhansali, CRND, ST Microelectronics, India. Design and development of Multiport memory generator.
12:00 to 12:30PM	M.C. Bhuvaneshwari and K. Shivanandam, PSG College of Technology, Testing Asynchronous Squential Circuits using Synchronous Model.		Dibya Dipti, Seema Jain, Nirmallya Kar, CRND, ST Microelectronics, India. Design and Development Small Size memory in 0.18 Micron technology.
12:30 to 1:00 PM	Raghuram, Texas Instruments (India), Automatic Functional Pattern Generation for Verification of FSMs and Interacting FSMs.
1:00 to 2:00 PM	Lunch
	Session T5 Trends in Testing Chair: Rajamohan Varambally, ST Microelectronics	Session L7 Low-Power Chair: Mahesh Mehendale, Texas Instruments	Session L8 Ideas in Logic Design Chair: M. Balakrishnan, IIT Delhi
2.00 to 2.30 PM	Vivek Agarwal et al., Texas Instruments (India), Scan Chain Reordering.	Vishal Dalal, Silicon Automation Systems, Software Power Optimizations in an Embedded System.	Debesh Das, Jadavpur University, H. Rahman, Jadavpur University, and B. Bhattacharya, ISI Calcutta. A New Synthesis of Symmetric Functions
2.30 to 3.00 PM	V.D. Agrawal, Bell Labs, Lucent Technologies, USA, Carlos  G. Parodi, Lucent Technologies, NJ, USA, and Jason David, NJIT, USA.  High-Speed VLSI Testing With Slow Test Application.	Rakesh Babu Bobba, Jais Abraham and Rubin A. Parekhji, Texas Instruments, India. Maximum Power Estimation Using Transition Fault ATPG.	Sacheendra Nath, Silicon Automation Systems. Faster Modular Multiplication in Hardware.
3.00 to 3.30 PM	Rajesh Kannah, ATI Tech. Fault Grading for Functional Testing of Microprocessors.		Kamran Nabi Khan, Controlnet India. Design and FPGA Implementation of Vector Quantization Circuit using VHDL.
3.30 to 4.00 PM	Tea
4.00 PM to 6.00 PM	Session L9 Panel Discussion : Challenges for VLSI Education in India Moderator: C.P. Ravikumar
Panelists: R. Srinivasan, ControlNet (Goa)  Prof. Vasagam, Tanitec (Chennai)  Dr. V. Ranganathan, Realchip (Chennai)  Prof. D. Nagchoudhuri, IIT Delhi  Dr. V.D. Agrawal, Bell Labs, USA.

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Physical Design Workshop

B. Bhattacharya, ISI Calcutta

Test Workshop

C.P. Ravikumar, IIT Delhi

Technical Program Committee

 

·Vishwani Agrawal, Lucent Technologies, USA ·Ashok Balivada, National Semiconductors, India ·Juergen Becker, Tech.l Univ. of Dormstadt, Germany ·Bhargab Bhattacharya, ISI Calcutta ·P.P. Chakrabarti, IIT Kharagpur, India ·Srimat Chakradhar, NEC, USA ·Kozo Kinoshita, Osaka University, Japan ·Anshul Kumar, IIT Delhi, India

·Ananta Majhi, Philips, Netherlands ·Mahesh Mehendale, Texas Instruments, India ·N.S. Murthy, IBM Global Services, India ·Dipankar Nagchoudhury, IIT Delhi, India ·C.P. Ravikumar, IIT Delhi ·Susmita Sur-Kolay, ISI Calcutta ·Alok Singh, Virage Logic, India ·Rajamohan Varambally, ST Microelectronics, India

Registration Information:
Registration permits you to participate in all the technical sessions and tutorials organized as part of the workshops.  Refreshments and lunch will be provided to all registrants at no extra charge.  Please send your registration fee through a draft  made out to VLSI Design and Test Workshops, 2000.   Make the  draft payable at Canara Bank, IIT Delhi Hauz Khas Branch.  The draft must be sent to Prof. C.P. Ravikumar, Department of Electrical Engineering,  Indian Institute of Technology, New Delhi, 110016, India.   If you wish to register on the spot,  drafts and cash  payment in Indian rupees are acceptable.   We will not be able to accept Foreign Currency or Credit Card payments.  The current exchange rate is approximately 1 US dollar = 45 Indian rupees.

Registration Fees Before July 20, 2000

	Indian Participant	Foreign Participant
Academic Institution	Rs. 2000	USD. 50
Non-academic Institution	Rs. 4000	USD. 150

Registration Fees After July 20, 2000

	Indian Participant	Foreign Participant
Academic Institution	Rs. 2500	USD. 75
Non-academic Institution	Rs. 4500	USD. 175

Venue Information:Contact numbers for The Habitat World are:+91 11 469-1920 and +91 11 469-1921.  FAX number is +91 11 460-2118.  Please ask for Ms Aarti Bhargava when inquiring about the workshops.  There are several Web sites that will give you information about travel and stay in New Delhi,  including www.delhizone.com.  A map showing the location of Habitat World in New Delhi is available at  www.iiefair.com/habitatmap.html .  Habitat World is located at Lodi Road, New Delhi and a pre-paid taxi from the air port to a hotel  around this area will cost Rs. 200 (About 5 US Dollars). You must enter from Gate 2.  Prepaid taxis can be hired at the airport itself.  Tipping the taxi driver is not necessary.  Alternative accommodation may be available in guest houses of organizations within New Delhi; you must contact the organizing chair before Aug 1, 2000 regarding this.

Weather Information:The weather in New Delhi in August is hot (temperatures ranging in 30 degrees to 35 degrees centigrade), with inermittent rain.  Umbrellas are recommended.

Contact Information: In case you have any questions, please contact C.P. Ravikumar (rkumar@ee.iitd.ernet.in) for clarifications.  E-mail can also be sent to vsiSecy@vlsi-india.org.

Fellowships: :A small number of full or partial waiver of registration fee is available for Indian students and Indian faculty.  Preference will be given to attendees who request for partial waiver.  Write to the organizing chair with a statement of purpose for attending the workshops before July 20, 2000.  Please note that travel support and staying arrangements will have to be made by the participant who avails the free registration.

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